Brad W Michael, 58Cedar Falls, IA

6421053, Jul 16, 2002

May 24, 1999

09/316097

Charles Ray Johns - Austin TX
John Samuel Liberty - Pflugerville TX
Brad William Michael - Cedar Park TX
John Fred Spannaus - Austin TX

International Business Machines Corporation - Armonk NY

G06T 1120

345441

Primitives are divided into span groups of 2N spans, and then processed in MÃN blocks of pixels, with the pixel blocks preferably being as close to square as possible and therefore optimized for small spans and texture mapping. Each span group is rendered block-by-block in a serpentine manner from an initial or entry block, first in a direction away from the long edge of the primitive and then in a direction towards the long edge. The interpolators include a one-deep stack onto which pixel and texel information for the initial or entry block are pushed before rendering any other blocks within the span group. Blocks or pairs of blocks within different span subgroups of the span group are then alternately rendered, such that rendering zig-zags between the span subgroups as it proceeds to the end of the span group. Once the first end of a span group is reached, the values for the initial or entry block are popped from the stack and rendering resumes from the initial or entry block in the opposite direction, but in the same serpentine or zig-zag manner, until the other end of the span group is reached. The next span group, if any, is rendered starting with a block adjacent to the last block rendered in the previous span group.

7149877, Dec 12, 2006

Jul 17, 2003

10/621908

Sang Hoo Dhong - Austin TX, US
Hwa-Joon Oh - Austin TX, US
Brad William Michael - Cedar Park TX, US
Silvia Melitta Mueller - St. Ingbert, DE
Kevin D. Tran - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 15/76

712 22, 712 2, 712221

A disclosed byte execution unit receives byte instruction information and two operands, and performs an operation specified by the byte instruction information upon one or both of the operands, thereby producing a result. The byte instruction specifies either a count ones in bytes operation, an average bytes operation, an absolute differences of bytes operation, or a sum bytes into halfwords operation. In one embodiment, the byte execution unit includes multiple byte units. Each byte unit includes multiple population counters, two compressor units, adder input multiplexer logic, adder logic, and result multiplexer logic. A data processing system is described including a processor coupled to a memory system. The processor includes the byte execution unit. The memory system includes a byte instruction, wherein the byte instruction specifies either the count ones in bytes operation, the average bytes operation, the absolute differences of bytes operation, or the sum bytes into halfwords operation.

7203608, Apr 10, 2007

Jun 16, 2006

11/424613

Makoto Aikawa - Tokyo, JP
Sang Hoo Dhong - Austin TX, US
Brian Flachs - Georgetown TX, US
Paul Marlan Harvey - Austin TX, US
Brad William Michael - Cedar Park TX, US
Yaping Zhou - Austin TX, US

International Business Machines Corporation - Armonk NY

G01R 27/28

702 57

A method for measuring impedance of a microprocessor chip, electronic packaging, and circuit board power supply system by generating a pseudo-impulse current having a width size in the time domain not larger than the inversion of a maximum frequency of interest and obtaining a voltage measurement in a frequency domain of the pseudo-impulse current. The mechanism of the present invention then predicts the normalized Fourier transformation of the current in the frequency domain, wherein the normalized Fourier transformation depends upon a switching charge of the pseudo-impulse current, measures the switching charge of the pseudo-impulse current, obtains a first current measurement at zero frequency using the measured switching charge, and obtains a second current measurement at a frequency of interest using the first current measurement. The mechanism of the present invention then calculates the impedance of the chip/package/board power supply system using the voltage measurement and the second current measurement.

7406589, Jul 29, 2008

May 12, 2005

11/127848

Sang Hoo Dhong - Austin TX, US
Gordon Clyde Fossum - Austin TX, US
Harm Peter Hofstee - Austin TX, US
Brad William Michael - Cedar Park TX, US
Silvia Melitta Mueller - Altdorf, DE
Hwa-Joon Oh - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 7/552
G06F 7/544
G06F 7/38

712222, 708495, 708508, 708500, 708502

High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.

7486096, Feb 3, 2009

Oct 31, 2006

11/554712

Sang H. Dhong - Austin TX, US
Brian Flachs - Georgetown TX, US
Gilles Gervais - Austin TX, US
Charles R. Johns - Austin TX, US
Brad W. Michael - Cedar Park TX, US
Makoto Aikawa - Tokyo, JP
Iwao Takiguchi - Tokyo, JP
Tetsuji Tamura - Tokyo, JP

International Business Machines Corporation - Armonk NY

G01R 31/26

324765, 324763

In one embodiment, a test system tests a device under test (DUT). The DUT includes an internal test controller that executes built-in self-test (BIST programs. Built-in self-test programs include array-based automatic built-in self-test programs, discrete and combinational logic built-in self-test programs, and functional architecture verification programs (AVPs). An external manufacturing system test controller manages the internal test controller within the DUT and determines minimum operating voltage levels for a power supply input voltage that supplies the DUT. A logic simulator provides a modeling capability to further enhance the development of minimum voltage power supply input operational values for the DUT.

7610531, Oct 27, 2009

Sep 13, 2006

11/531287

Sang H. Dhong - Austin TX, US
Brian Flachs - Georgetown TX, US
Gilles Gervais - Austin TX, US
Brad W. Michael - Cedar Park TX, US
Mack W. Riley - Austin TX, US

International Business Machines Corporation - Armonk NY

G01R 31/28

714724, 714726, 714728, 714729, 714738, 714739

Mechanisms for modifying a test pattern to control power supply noise are provided. A portion of a sequence of states in a test sequence of a test pattern waveform is modified so as to achieve a circuit voltage, e. g. , an on-chip voltage, which approximates a nominal circuit voltage, such as produced by the application of other portions of the sequence of states in the same or different test sequences. For example, hold state cycles or shift-scan state cycles may be inserted or removed prior to test state cycles in the test pattern waveform. The insertion/removal shifts the occurrence of the test state cycles within the test pattern waveform so as to adjust the voltage response of the test state cycles so that they more closely approximate a nominal voltage response. In this way, false failures due to noise in the voltage supply may be eliminated.

7870308, Jan 11, 2011

Dec 23, 2008

12/342280

Brian K. Flachs - Georgetown TX, US
Charles R. Johns - Austin TX, US
John S. Liberty - Round Rock TX, US
Brad W. Michael - Cedar Park TX, US

International Business Machines Corporation - Armonk NY

G06F 13/14

710 22, 711215

A mechanism for programming a direct memory access engine operating as a single thread processor is provided. A program is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the program located in the local memory is to be executed. The direct memory access engine executes the program without intervention by a host processor. Responsive to the program completing execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.

7870309, Jan 11, 2011

Dec 23, 2008

12/342501

Brian K. Flachs - Georgetown TX, US
Harm P. Hofstee - Austin TX, US
Charles R. Johns - Austin TX, US
Matthew E. King - Pflugerville TX, US
John S. Liberty - Round Rock TX, US
Brad W. Michael - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 13/14

710 22, 711215

A mechanism programming a direct memory access engine operating as a multithreaded processor is provided. A plurality of programs is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the plurality of programs located in the local memory is to be executed. The direct memory access engine executes two or more of the plurality of programs without intervention by a host processor. As each of the two or more of the plurality of programs completes execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.