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Bradley J Boland, 52Anderson, SC

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Anderson, SC   

Hawthorne, FL   

Waddell, AZ   

19210 S Mitkof Loop, Eagle River, AK 99577    907-2291529   

18823 Sarichef Loop, Eagle River, AK 99577   

Glendale, AZ   

Elmendorf AFB, AK   

Sheppard AFB, TX   

Jber, AK   

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Publications & IP owners

Us Patents

Semiconductor Package Having Multiple Dies With Independently Biased Back Surfaces

US Patent:
6396130, May 28, 2002
Filed:
Sep 14, 2001
Appl. No.:
09/953422
Inventors:
Sean T. Crowley - Phoenix AZ
Bradley D. Boland - Gilbert AZ
Assignee:
Amkor Technology, Inc. - Chandler AZ
International Classification:
H01L 23495
US Classification:
257666, 257675, 257706, 257707
Abstract:
A thin, thermally efficient, lead frame-type of semiconductor package incorporating multiple dies includes a plurality of electrically conductive leads held together in a spaced, planar relationship about a central opening defined by the leads, and a plurality of thick, plate-like heat sinks supported within the opening such they are generally coplanar with each other, parallel to the plane of the leads, and electrically isolated from the leads and each other. Each of the heat sinks has a lower surface that can be exposed through the outer surface of a molded resin envelope encapsulating the package for the efficient dissipation of heat therefrom, and an upper surface having a recess formed into it. A semiconductor die is mounted in each of the recesses with its back surface in electrical connection with the floor of the recess. Each recess defines a wire bonding ring around the periphery of the upper surface of the respective heat sink immediately adjacent to the edges of the corresponding die for the bonding thereto of wires from the die and/or the leads.

Packaging High Power Integrated Circuit Devices

US Patent:
6521982, Feb 18, 2003
Filed:
Jun 2, 2000
Appl. No.:
09/587136
Inventors:
Sean T. Crowley - Phoenix AZ
Blake A. Gillett - Gilbert AZ
Bradley D. Boland - Mesa AZ
Assignee:
Amkor Technology, Inc. - Chandler AZ
International Classification:
H01L 23495
US Classification:
257676, 257666, 257692, 257735, 257696, 257698, 257712, 257717, 257673, 257401, 257329, 257139, 257341, 257675
Abstract:
The invention provides a method and apparatus for electrically connecting the die of a high power semiconductor device to a substrate with a conductive strap such that the connection is resistant to the shear stresses resulting with changes in temperature. In one embodiment, the method includes providing a substrate having first and second portions that are electrically isolated from each other. A semiconductor die having top and bottom surfaces and one or more active electronic devices formed therein is also provided. The device has a first terminal connected to a first conductive layer on the bottom surface of the die, and a second terminal connected to a second conductive layer on the top surface of the die. The first conductive layer is electrically coupled to a top surface of the first portion of the substrate. The second conductive layer is electrically coupled to the second portion of the substrate with a metal strap.

Power Semiconductor Package With Strap

US Patent:
6630726, Oct 7, 2003
Filed:
Nov 7, 2001
Appl. No.:
10/008048
Inventors:
Sean T. Crowley - Phoenix AZ
William M. Anderson - Gilbert AZ
Bradley D. Boland - Gilbert AZ
Eelco Bergman - Sunnyvale CA
Assignee:
Amkor Technology, Inc. - Chandler AZ
International Classification:
H01L 2348
US Classification:
257666, 257692, 257668, 361813
Abstract:
A semiconductor package and a method for fabricating a semiconductor package are disclosed. In one embodiment, the semiconductor package includes an exposed portion of a conductive strap at a package horizontal first surface and exposed surfaces of multiple leads at a package horizontal second surface. A power semiconductor die is mounted on a die pad connected to at least one lead having an exposed surface. Heat generated by the die within the package may be dissipated through thermal paths including the exposed surfaces.

Semiconductor Device Including Metal Strap Electrically Coupled Between Semiconductor Die And Metal Leadframe

US Patent:
6707138, Mar 16, 2004
Filed:
Sep 26, 2002
Appl. No.:
10/256905
Inventors:
Sean T. Crowley - Phoenix AZ
Blake A. Gillett - Gilbert AZ
Bradley D. Boland - Mesa AZ
Philip S. Mauri - Cabuyao, PH
Ferdinand E. Belmonte - Laguna, PH
Remigio V. Burro, Jr. - San Pedro, PH
Victor M. Aquino, Jr. - Marikina, PH
Assignee:
Amkor Technology, Inc. - Chandler AZ
International Classification:
H01L 2348
US Classification:
257676, 257666, 257692, 257735, 257696, 257698, 257712, 257717, 257673, 257401, 257329, 257139, 257341, 257675
Abstract:
A semiconductor device is disclosed that includes a semiconductor die, a metal leadframe, and a metal strap. A bottom surface of the semiconductor device is on and electrically coupled to a first portion of the leadframe. A first end portion of the metal strap is on and electrically coupled to a top surface of the semiconductor die. An opposite, second end portion of the metal strap is on and electrically coupled to a second portion of the leadframe within a recess of the second portion of the leadframe.

Making Two Lead Surface Mounting High Power Microleadframe Semiconductor Packages

US Patent:
6756658, Jun 29, 2004
Filed:
Apr 6, 2001
Appl. No.:
09/827791
Inventors:
Blake A. Gillett - Gilbert AZ
Sean T. Crowley - Phoenix AZ
Bradley D. Boland - Gilbert AZ
Keith M. Edwards - Phoenix AZ
Assignee:
Amkor Technology, Inc. - Chandler AZ
International Classification:
H01L 23495
US Classification:
257666, 257669, 257670, 257674, 257676
Abstract:
A two-lead, surface-mounting, high-power micro-leadframe semiconductor package has the same outline, mounting, and electrical functionality as industry standard leadframe packages but provides a lower internal resistance, a higher package power rating, and costs less to produce. The novel package incorporates one of a rectangular array of âmicro-leadframesâ (âMLFsâ), each having parallel and respectively coplanar upper and lower surfaces etched in a plate having a uniform thickness. Each micro-leadframe includes an I-shaped die pad having a head, a foot, and opposite sides. First and second leads are disposed at the foot of the die pad, each having a side aligned with one of the sides of the pad. The second lead has an right-angled wire-bonding pad next to the die pad. A portion of a lower surface of each of the die pad and the leads is exposed through a lower surface of an envelope of plastic molded on the package to define package input/output terminals.

Power Semiconductor Package With Strap

US Patent:
6873041, Mar 29, 2005
Filed:
Jul 11, 2003
Appl. No.:
10/618192
Inventors:
Sean T. Crowley - Phoenix AZ, US
William M. Anderson - Gilbert AZ, US
Bradley D. Boland - Gilbert AZ, US
Eelco Bergman - Sunnyvale CA, US
Assignee:
Amkor Technology, Inc. - Chandler AZ
International Classification:
H01L023/48
H01L023/52
US Classification:
257692, 257693, 257687, 257690
Abstract:
A semiconductor package and a method for fabricating a semiconductor package are disclosed. In one embodiment, the semiconductor package includes an exposed portion of a conductive strap at a package horizontal first surface and exposed surfaces of multiple leads at a package horizontal second surface. A power semiconductor die is mounted on a die pad connected to at least one lead having an exposed surface. Heat generated by the die within the package may be dissipated through thermal paths including the exposed surfaces.

Thin Leadframe-Type Semiconductor Package Having Heat Sink With Recess And Exposed Surface

US Patent:
6198163, Mar 6, 2001
Filed:
Oct 18, 1999
Appl. No.:
9/420065
Inventors:
Sean Timothy Crowley - Phoenix AZ
Bradley David Boland - Mesa AZ
Assignee:
Amkor Technology, Inc. - Chadler AZ
International Classification:
H01L 2310
H01L 2334
H01L 2940
H01L 2348
H05K 720
US Classification:
257706
Abstract:
A thin, small-outline semiconductor package, and a thermally enhanced leadframe for use in it, comprise a plurality of electrically conductive leads held together in a spaced, planar relationship about a central opening defined by the leads, and a thick, plate-like heat sink made of an electrically and thermally conductive metal attached to the leads such that it is centered within the opening and parallel to the plane of the leads. The heat sink has a lower surface exposed through the outer surface of a molded resin envelope encapsulating the package for the efficient dissipation of heat therefrom, and an upper surface having a recess formed into it. The recess has a planar floor with a semiconductor die attached to it, and defines a grounding ring around the periphery of the upper surface of the heat sink immediately adjacent to the edges of the die for the down-bonding of grounding wires from the die and the leads. The package provides enhanced heat dissipating capabilities, an improved resistance to long-term penetration by moisture, and a down-bonding region that substantially shortens the length of grounding wires down-bonded thereto and substantially reduces the residual shear stress acting on the down-bonds.

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