Brian J Archer, 33Los Angeles, CA

2021024, Aug 5, 2021

Jan 26, 2021

17/159017

- Mountain View CA, US
Brian Archer - Mountain View CA, US

G06F 30/398

To specifically identify faults within a semiconductor cell, a SPICE netlist associated with the semiconductor cell design is retrieved, and one or more transistor characteristics are identified within the SPICE netlist. An advanced cell-aware fault model is executed for the semiconductor cell, and results are returned for one or more fault test methods of the advanced cell-aware fault model for a cell of the semiconductor chip design. A method for identifying faults within the semiconductor cell continues by correlating one more faults detected as a result of the fault test methods with one or more transistor characteristics within the SPICE netlist, and a user interface is generated for identifying one or more faulty transistors within the semiconductor chip design.

2018003, Feb 8, 2018

Aug 5, 2016

15/230079

- Mountain View CA, US
Brian Matthew Archer - Mountain View CA, US
William Albert Lloyd - Beaverton OR, US
Christopher Kevin Allsup - Sunnyvale CA, US
Xiaolei Cai - Portland OR, US
Kevin Chau - San Jose CA, US

G06F 17/50

A computer-implemented method for characterizing a circuit is presented. The method includes receiving, by the computer, data representative of the circuit and at least one defect of the circuit. The method further includes simulating, using the computer, the circuit to obtain a first timing characteristic, and simulating, using the computer, the circuit with the at least one defect to obtain a second timing characteristic. The method further includes identifying, using the computer, an association between at least one test vector and the at least one defect in accordance with the first timing characteristic, the second timing characteristic, and a multitude of strobes applied during a first time interval associated with the at least one test vector, when the computer is invoked to characterize the circuit.