Brian M Leitner, 454730 SE Kelly St, Portland, OR 97206

6775719, Aug 10, 2004

Sep 28, 2000

09/671703

Brian M. Leitner - Hillsboro OR
Dominic J. Gasbarro - Forest Grove OR
Jie Ni - Portland OR
Tom E. Burton - Vancouver WA

Intel Corporation - Santa Clara CA

G06F 1300

710 33, 710 51, 370399, 370463

A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter comprises a host interface arranged to interface a host memory of the host system; a serial interface arranged to receive and transmit data from said switched fabric; a Micro-Engine (ME) arranged to work on multiple tasks based on a Virtual Interface (VI) to support data transfers via the switched fabric, and configured to issue a host request to said host interface for a host transaction including an address and length of host data to be fetched from the host memory, and an End-Of-Cell (EOC) indicator which indicates that a cell has been built for transmission via the serial interface, and to begin working on a different task without waiting for the corresponding host response of the host request from the host interface; a Scheduler arranged to supply a request and a request VI number to said Micro-Engine (ME) for work; and a Request Comparator arranged to check the current VI that is being worked on by the Micro-Engine (ME), and to generate an acknowledgment ACK or a negative acknowledgment NACK to the Scheduler depending upon whether the request VI number is currently being worked on by the Micro-Engine (ME).

6778548, Aug 17, 2004

Jun 26, 2000

09/603957

Tom E. Burton - Beaverton OR
Dominic J. Gasbarro - Forest Grove OR
Brian M. Leitner - Hillsboro OR
Dean S. Susnow - Portland OR

Intel Corporation - Santa Clara CA

H04L 1254

370429, 370360

A device to create, receive, and transmit packets of data in a packet switching network. This device employs a direct memory access packet controller which would interface between memory contained within a computer system and a packet switched network. This direct memory access packet controller would utilize one or more micro-engines that would dynamically allocate buffer space to process received packets of data. This direct memory access packet controller would further utilize a transmit cell FIFO circuit to allocate buffer space to packets being transmitted. In addition, a sequencer would act to control the workflow of packets being received and transmitted.

6831916, Dec 14, 2004

Sep 28, 2000

09/671707

Balaji Parthasarathy - Hillsboro OR, 97124
Dominic J. Gasbarro - Forest Grove OR, 97116
Tom E. Burton - Beaverton OR, 97006
Brian M. Leitner - Hillsboro OR, 97124

H04L 1266

370359, 370389, 370429, 370463, 710 4, 710 22, 710 52, 710 73, 712221

A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter comprises a micro-controller subsystem configured to establish connections and support data transfers via the switched fabric, and a serial interface which provides an interface with the switched fabric. The micro-controller subsystem includes a Micro-Engine (ME) which executes a ME instruction to send source and destination addresses during a control cycle, and interface logic blocks which supply addressed data from designated sources to the Micro-Engine (ME) at the same time for execution of the ME instruction during a data cycle subsequent to the control cycle.

6917987, Jul 12, 2005

Mar 26, 2001

09/816344

Balaji Parthasarathy - Hillsboro OR, US
Dominic J Gasbarro - Forest Grove OR, US
Brian M. Leitner - Hillsboro OR, US

Intel Corporation - Santa Clara CA

G06F013/00

709249

A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter may comprise at least one Micro-Engine (ME) arranged to establish connections and support data transfer operations via a switched fabric; a serial interface arranged to receive and transmit data packets from the switched fabric for data transfer operations; a host interface arranged to receive and transmit host data transfer work requests from the host system for data transfer operations; a context memory arranged to provide context information necessary for data transfer operations; a doorbell manager arranged to update the context information needed for the Micro-Engine (ME) to process host data transfer requests for data transfer operations; and, a remote key manager arranged to manage remote keys and check the validity of the remote keys which correspond to outstanding data transfer operations.

6961837, Nov 1, 2005

Mar 25, 2003

10/396585

Ken C. Haren - Portland OR, US
Lee Albion - Portland OR, US
Brian M. Leitner - Hillsboro OR, US
Dominic J. Gasbarro - Forest Grove OR, US

Intel Corporation - Santa Clara CA

G06F012/10

711202, 711204, 711213, 710 52, 710 56

An end of a queue or a page-crossing within a queue is detected. A virtual memory address for the head of the queue or for the next queue page is pre-translated into a physical memory address while the last entry in the queue or in the current queue page is being serviced.

7107359, Sep 12, 2006

Oct 30, 2000

09/698188

Tom E. Burton - Beaverton OR, US
Dominic J. Gasbarro - Forest Grove OR, US
Brian M. Leitner - Hillsboro OR, US

Intel Corporation - Santa Clara CA

G06F 15/16
G06F 15/76
H04L 12/66
G06F 13/14

709250, 712 34, 712 36, 370463, 710305

A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter may comprise a Micro-Engine (ME) arranged to establish connections and support data transfers via a switched fabric; a serial interface arranged to receive and transmit data packets from the switched fabric for data transfers; a host interface arranged to receive and transmit host data transfer requests, in the form of descriptors, from the host system for data transfers; a Receiver Header Hardware Assist (HWA) Mechanism configured to check header information of incoming data packets host descriptors for header errors so as to offload the Micro-Engine (ME) from having to check for header errors; and a Transmitter Header Hardware Assist (HWA) Mechanism configured to generate OpCode and Length fields for an outgoing data packet when an entire data packet is being assembled for transmission, via the serial interface, so as to offload the Micro-Engine (ME) from having to build all data packets for data transfers.

7181541, Feb 20, 2007

Sep 29, 2000

09/672711

Tom E. Burton - Beaverton OR, US
Dominic J. Gasbarro - Forest Grove OR, US
Brian M. Leitner - Hillsboro OR, US

Intel Corporation - Santa Clara CA

G06F 15/16
G06F 15/76
G06F 13/14
H04L 12/66

709250, 712 34, 712 36, 710305, 370463

A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter may comprise a Micro-Engine (ME) arranged to establish connections and support data transfers via a switched fabric; a host interface arranged to receive and transmit host data transfer requests, in the form of descriptors, from the host system for data transfers, and incorporated therein a host interface Hardware Assist (HWA) mechanism configured to pre-process host descriptors for descriptor format errors in parallel with descriptor fetches so as to offload the Micro-Engine (ME) from exclusively checking for descriptor format errors; a serial interface arranged to receive and transmit data packets from the switched fabric for data transfers; and a first-in/first-out (FIFO) interface arranged to receive and transmit data packets to/from the switched fabric via the serial interface, and incorporated therein a Protection Index and Offset Hardware Assist (HWA) mechanism configured to process the Virtual Address (VA) and Memory Handle (MH) of data packets and generate therefrom a Protection Index (PI) and Offset so as to offload said Micro-Engine (ME) from exclusively processing data packets for data transfers.

7352763, Apr 1, 2008

Jan 20, 2004

10/761394

Tom E. Burton - Beaverton OR, US
Dominic J. Gasbarro - Forest Grove OR, US
Brian M. Leitner - Hillsboro OR, US
Dean S. Susnow - Portland OR, US

Intel Corporation - Santa Clara CA

H04L 12/56
H04L 29/06
H05L 12/28

370412, 370360, 370389, 37039554, 709250

A device to create, receive, and transmit packets of data in a packet switching network. This device employs a direct memory access packet controller which would interface between memory contained within a computer system and a packet switched network. This direct memory access packet controller would utilize one or more micro-engines that would dynamically allocate buffer space to process received packets of data. This direct memory access packet controller would further utilize a transmit cell FIFO circuit to allocate buffer space to packets being transmitted. In addition, a sequencer would act to control the workflow of packets being received and transmitted.