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Charles F Simmers Deceased12418 W Galaxy Dr, Sun City West, AZ 85375

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Sun City West, AZ   

Peoria, AZ   

Ruskin, FL   

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Charles F Simmers

Address:
Sun City, AZ 85351
Licenses:
License #: PE008693L - Expired
Category: Engineers
Type: Professional Engineer

Publications & IP owners

Us Patents

Three-Color Rgb Led Color Mixing And Control By Variable Frequency Modulation

US Patent:
8339058, Dec 25, 2012
Filed:
Nov 23, 2009
Appl. No.:
12/623657
Inventors:
Charles R. Simmers - Phoenix AZ, US
Assignee:
Microchip Technology Incorporated - Chandler AZ
International Classification:
H05B 41/16
US Classification:
315246, 315152, 315250
Abstract:
Perceived output color and intensity (brightness) of light from a three-element red-green-blue (RGB) light emitting diode (LED) or optical combination of three LEDs (red, green and blue) are controlled with three pulse train signals, each having fixed pulse width and voltage amplitude and then increasing or decreasing the frequency (increasing or decreasing the number of pulses over a time period) of these pulse train signals so as to vary the average current through each of the RGB-LEDs. This reduces the level of electro-magnetic interference (EMI) at any one frequency by varying the pulse train energy spectrum over a plurality of frequencies.

Led Brightness Control By Variable Frequency Modulation

US Patent:
8339068, Dec 25, 2012
Filed:
Oct 9, 2009
Appl. No.:
12/576346
Inventors:
Charles R. Simmers - Phoenix AZ, US
Assignee:
Microchip Technology Incorporated - Chandler AZ
International Classification:
G06F 1/00
H05B 37/02
H05B 39/04
H05B 41/36
US Classification:
315297, 315158, 315291
Abstract:
Perceived intensity (brightness) of light from a light emitting diode (LED) is controlled with a pulse train signal having fixed pulse width and voltage amplitude and then increasing or decreasing the frequency (increasing or decreasing the number of pulses over a time period) of this pulse train signal so as to vary the average current through the LED. This reduces the level of electro-magnetic interference (EMI) at any one frequency by varying the pulse train energy spectrum over a plurality of frequencies.

Debugging Embedded Systems

US Patent:
2002014, Oct 3, 2002
Filed:
Mar 30, 2001
Appl. No.:
09/822739
Inventors:
Charles Simmers - Phoenix AZ, US
Joseph Triece - Phoenix AZ, US
International Classification:
G06F009/44
US Classification:
717/124000
Abstract:
An embedded system is provided with the capability to be debugged. The embedded system includes a central processing unit (CPU) that is coupled to a bus having certain contents. A register, also with contents, is available for loading by the CPU. Finally, a debug logic circuit is also included. The debug logic circuit is coupled to both the bus and the CPU. The debug circuit itself is composed of a breakpoint detect circuit that is coupled to the bus and to the register. This circuitry enables a breakpoint signal that is produced by the breakpoint detect circuit when the contents of the register equal the contents of the bus. A method is also provided for debugging an embedded system having a microcontroller with a CPU. First, a debug logic circuit that resides on the same chip as the microcontroller is programmed to detect a predetermined condition in the microcontroller. Next, application software is run on the microcontroller. When a predetermined condition is detected, the CPU is interrupted which provides the ability to view the condition of the microcontroller. Programming the debug logic circuit can include the storing of a breakpoint address in a breakpoint address register. Afterward, a program memory address bus is selected for comparison to the contents of the breakpoint address register, upon which time a breakpoint counter is set to zero. The steps of interrupting and detecting are accomplished by comparing the contents of the program memory address bus to the contents of the breakpoint register and, if they are equal, then the CPU is interrupted.

Reducing Power Consumption And Bus Bandwidth Requirements In Cellular Phones And Pdas By Using A Compressed Display Cache

US Patent:
5907330, May 25, 1999
Filed:
Dec 18, 1996
Appl. No.:
8/768427
Inventors:
Charles R. Simmers - Phoenix AZ
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G09G 500
US Classification:
345512
Abstract:
A method and apparatus for reducing power consumption and system bus load caused by a display controller in a unified memory system. A compression engine monitors a bus over which display data from the unified memory flows. The compression engine captures and compresses a copy of the display data corresponding to a display frame. The compressed data is stored in a small memory unit. Subsequent refreshes of the display are serviced by a decompression engine. The decompression engine decompresses the compressed data from the small memory unit and provides the decompressed data to the display controller.

Reducing Power Consumption And Bus Bandwidth Requirements In Cellular Phones And Pdas By Using A Compressed Display Cache

US Patent:
6075523, Jun 13, 2000
Filed:
Jan 26, 1999
Appl. No.:
9/237575
Inventors:
Charles R. Simmers - Phoenix AZ
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06T 900
US Classification:
345202
Abstract:
A method and apparatus for reducing power consumption and system bus load caused by a display controller in a unified memory system. A compression engine monitors a bus over which display data from the unified memory flows. The compression engine captures and compresses a copy of the display data corresponding to a display frame. The compressed data is stored in a small memory unit. Subsequent refreshes of the display are serviced by a decompression engine. The decompression engine decompresses the compressed data from the small memory unit and provides the decompressed data to the display controller.

Application Of Split- And Dual-Screen Lcd Panel Design In Cellular Phones

US Patent:
5841431, Nov 24, 1998
Filed:
Nov 15, 1996
Appl. No.:
8/749486
Inventors:
Charles Russell Simmers - Phoenix AZ
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G09G 500
G09G 336
G06F 100
G06F 116
US Classification:
345211
Abstract:
An apparatus for conserving power in information devices with dual functions. A single display panel is logically split into two sub-panels. Each sub-panel can be powered up or down separately as is required by the function of the device. The display panel has a plurality of improved segment drivers which are provided power signals enabling the set of segment drivers corresponding to a sub-panel to be separately powered. In systems with two separate display panels, each of the panels may be powered up or down by the use of similar improved segment drivers as necessary.

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