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Brion N Shimamoto, 77343 Riverside Ave, Riverside, CT 06878

Brion Shimamoto Phones & Addresses

343 Riverside Ave, Riverside, CT 06878    203-6371443    203-6372154   

1465 Putnam Ave, Old Greenwich, CT 06870   

343 Riversville Rd, Greenwich, CT 06831    203-6371443   

343 Riversville Rd, Greenwich, CT 06831    203-9277868   

Mentions for Brion N Shimamoto

Publications & IP owners

Us Patents

Method And System For Managing And Configuring Virtual Private Networks

US Patent:
7181542, Feb 20, 2007
Filed:
Mar 22, 2001
Appl. No.:
09/814178
Inventors:
Mark Tuomenoksa - Winchester MA, US
Samuel Bendinelli - Princeton NJ, US
Jerold Francus - Far Hills NJ, US
Jonathan Harwood - Rumson NJ, US
Michael Herrick - Colts Neck NJ, US
John Keane - Metuchen NJ, US
Christopher Macey - Red Bank NJ, US
Brion Shimamoto - Riverside CT, US
Assignee:
Corente, Inc. - East Brunswick NJ
International Classification:
H04I 9/00
US Classification:
709250, 709227, 709238, 713153, 713168
Abstract:
Methods and systems are provided for enabling a network between a first and a second processor using at least one additional processor separate from the first and second processors. In one embodiment, the at least one additional processor receives information indicating a consent on behalf of the first processor to enabling a tunnel between the first processor and the second processor and receives information indicating a consent on behalf of the second processor to enabling a tunnel between the second processor and the first processor. The at least one additional processor determines a first virtual address for the first processor and a second virtual address for the second processor such that the first and second virtual addresses uniquely identify the first and second processors, respectively, and are routable through the network. The at least one additional processor provides to each of the first and second processors the first and second virtual addresses to enable one or more tunnels between the first and the second processors.

Methods And System For Providing Network Services Using At Least One Processor Interfacing A Base Network

US Patent:
7181766, Feb 20, 2007
Filed:
Apr 11, 2001
Appl. No.:
09/832345
Inventors:
Samuel Bendinelli - Princeton NJ, US
Michael Herrick - Colts Neck NJ, US
John Keane - Metuchen NJ, US
Christopher Macey - Red Bank NJ, US
Mark Tuomenoksa - Winchester MA, US
Jerold Francus - Far Hills NJ, US
Jonathan Harwood - Rumson NJ, US
Brion Shimamoto - Riverside CT, US
Joseph Ferraro - Old Tappan NJ, US
Assignee:
Corente, Inc. - East Brunswick NJ
International Classification:
G06F 15/177
H04L 9/00
G06F 3/00
US Classification:
726 15, 726 3, 726 4, 709220, 709223, 710 1, 713151, 713152, 713153
Abstract:
Methods and systems are provided for providing network services using at least one processor, such as a network operations center that interfaces a base network. The network operations center may receive information identifying a user authorized to administer a first processor, which may be separate from the network operations center, and a base address that is routable in the base network. The network operations center may provide through the base network code and information for self-configuring the first processor as a gateway that interfaces the base network at the base address. The first processor may execute the provided code to self-configure itself as the gateway based on the provided information. The network operations center may then provide through the base network to the first processor additional information enabling at least one tunnel through the base network to a second processor, which may also be separate from the network operations center, when the first and second processors each provide to the network operations center a consent for enabling the tunnel.

Microprocessor Implemented Data Processing System Capable Of Emulating Execution Of Special Instructions Not Within The Established Microprocessor Instruction Set By Switching Access From A Main Store Portion Of A Memory

US Patent:
4972317, Nov 20, 1990
Filed:
Aug 4, 1989
Appl. No.:
7/390454
Inventors:
Joseph P. Buonomo - Endicott NY
Robert W. Callahan - Endwell NY
Steven R. Houghtalen - Endicott NY
Sivarama K. Kodukula - Binghamton NY
Raymond E. Losinger - Endicott NY
Brion N. Shimamoto - Greenwich CT
Harry L. Tredennick - San Jose CA
James W. Valashinas - Endicott NY
Assignee:
International Business Machines Corp. - Armonk NY
International Classification:
G06F 1500
US Classification:
364200
Abstract:
A microprocessor chip which is capable of executing a specific subset of instructions on behalf of the main storage portion of a computer memory can be made to emulate direct execution instructions not in that specific subset while working on behalf a control storage portion of the computer memory in a manner which is transparent to the main storage portion by means of a novel set of operand space selection instructions in the control storage portion and a novel switching circuit on the microprocessor chip which controls the access of the chip to the control store portion and the main store portion.

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