Bruce Edward Beattie, 64Beaverton, OR

6465358, Oct 15, 2002

Oct 6, 2000

09/684550

Michael S. Nashner - Beaverton OR
Bruce Beattie - Portland OR

Intel Corporation - Santa Clara CA

H01L 21311

438700, 438906, 438963, 438750, 438751, 438638

An improved method of forming a semiconductor device is described. The method comprises forming a dielectric layer on a substrate, forming a photoresist layer on the dielectric layer, then patterning the photoresist layer to define a region to be etched. After forming an etched region within the dielectric layer, the photoresist layer is removed and the etched region is cleaned. The etched region is cleaned by applying a buffered oxide etch dip, followed by an amine based dip.

6597046, Jul 22, 2003

Aug 20, 1999

09/378053

Robert S. Chau - Beaverton OR
Reza Arghavani - Aloha OR
Bruce Beattie - Portland OR

Intel Corporation - Santa Clara CA

H01L 2976

257411, 257406, 257410, 438216, 438261, 438287, 438591

An integrated circuit includes insulated gate field effect transistors (IGFETs), having gate dielectric layers wherein a nitrogen concentration in the gate dielectric varies between a first concentration at the gate electrode/gate dielectric interface and a second concentration at the gate dielectric/substrate interface. In one embodiment the gate dielectric is an oxynitride formed by an N plasma; and the oxynitride has top surface nitrogen concentration that is higher than a bottom surface nitrogen concentration. In a further aspect of the present invention, an integrated circuit includes a plurality of IGFETs, wherein various ones of the plurality of IGFETs have different gate dielectric thicknesses and compositions. A method of forming IGFETs with different gate dielectric thicknesses and compositions, on a single integrated circuit, includes forming a first oxynitride layer, forming a masking layer, removing a portion of the first oxynitride layer, forming an oxide layer where the oxynitride was removed, and forming a plurality of gate electrodes, a first portion of the gate electrodes overlying the first oxynitride layer.

2005015, Jul 21, 2005

Jan 21, 2004

10/761392

Vani Thirumala - San Jose CA, US
Nabil Mistkawi - Keizer OR, US
Bruce Beattie - Portland OR, US
John O'Sullivan - CO. Weath, IE
Huiying Liu - Sunnyvale CA, US
Noriko Oshiro - San Jose CA, US
Hokkin Choi - San Jose CA, US
Loretta Cordrey - Livermore CA, US

H01L021/302
H01L021/461

438745000

By providing a silicon containing precursor, such as methyl triethoxysilane, to a phosphoric etch bath, wafers containing nitride may be selectively etched without unduly impacting other silicon containing underlying layers.

2008015, Jun 26, 2008

Dec 22, 2006

11/644432

Ming Fang - Portland OR, US
Steve Keating - Beaverton OR, US
Vani Thirumala - San Jose CA, US
Lin Sha - Portland OR, US
Bruce Beattie - Portland OR, US

B05D 3/00
B08B 7/00
C11D 7/00

427299, 106 1405, 134 42, 510175

Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming a thin metal-organic layer on a copper structure, wherein the thin metal-organic layer substantially prevents corrosion of the copper structure, and wherein the thin metal-organic layer comprises an organo-copper compound comprising an alkyl group and a thiol group. In addition, methods of applying a high pH cleaning process using a surfactant to improve surface wetting in a low foaming solution is described.

6124171, Sep 26, 2000

Sep 24, 1998

9/160556

Reza Arghavani - Aloha OR
Bruce Beattie - Portland OR
Robert S. Chau - Beaverton OR
Jack Kavalieros - Portland OR
Bob McFadden - Aloha OR

Intel Corporation - Santa Clara CA

H01L 21336

438286

Transistors are formed on the substrate having two different thickness' of gate oxides. A silicon nitride mask is used to protect one of the gate oxides while the other is grown. A nitride mask is formed from a hydrogen balanced nitride layer formed using direct plasma deposited nitride with an ammonia and silane chemistry. In one embodiment the nitride mask remains in place in the completed transistor.

6087236, Jul 11, 2000

Nov 24, 1998

9/198831

Robert S. Chau - Beaverton OR
Reza Arghavani - Aloha OR
Bruce Beattie - Portland OR

Intel Corporation - Santa Clara CA

H01L 21336
H01L 218238

438301

An integrated circuit includes insulated gate field effect transistors (IGFETs), having gate dielectric layers wherein a nitrogen concentration in the gate dielectric varies between a first concentration at the gate electrode/gate dielectric interface and a second concentration at the gate dielectric/substrate interface. In one embodiment the gate dielectric is an oxynitride formed by an N. sub. 2 plasma; and the oxynitride has top surface nitrogen concentration that is higher than a bottom surface nitrogen concentration. In a further aspect of the present invention, an integrated circuit includes a plurality of IGFETs, wherein various ones of the plurality of IGFETs have different gate dielectric thicknesses and compositions. A method of forming IGFETs with different gate dielectric thicknesses and compositions, on a single integrated circuit, includes forming a first oxynitride layer, forming a masking layer, removing a portion of the first oxynitride layer, forming an oxide layer where the oxynitride was removed, and forming a plurality of gate electrodes, a first portion of the gate electrodes overlying the first oxynitride layer.

4909185, Mar 20, 1990

Feb 3, 1988

7/151954

Robert E. Aldridge - Beaverton OR
Bruce E. Beattie - Portland OR

Weiss Scientific Glass Blowing Co.

C23C 800

118729

Apparatus for heating product with the product during heating subjected to a controlled, nonatmospheric gas environment. The apparatus includes a double-walled cold zone assembly adapted to be placed against an oven opening, the assembly having a depository chamber within it for securing product during cooling of the product. A cantilever projecting through the assembly is operated to move product between the depository chamber of the assembly and the oven where heat treatment occurs.

2022024, Aug 4, 2022

Apr 20, 2022

17/725471

- Santa Clara CA, US
Biswajeet GUHA - Hillsboro OR, US
Leonard GULER - Hillsboro OR, US
Souvik CHAKRABARTY - Hillsboro OR, US
Jun Sung KANG - Portland OR, US
Bruce BEATTIE - Portland OR, US
Tahir GHANI - Portland OR, US

INTEL CORPORATION - Santa Clara CA

H01L 29/06
H01L 21/8238
H01L 29/423
H01L 29/66
H01L 29/78

A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.