Bruce Y Chang, 43Elk Grove, CA

2014002, Jan 30, 2014

Jul 26, 2012

13/559292

Bruce J. Chang - Saratoga CA, US
Damien Walker - San Jose CA, US
Bruce Petrick - Sunnyvale CA, US

ORACLE INTERNATIONAL CORPORATION - Redwood City CA

H04L 12/56

370392

Systems and methods that allow for dynamically deconfiguring, reconfiguring and/or otherwise configuring nodes (e.g., processors) in a symmetric multiprocessing system (e.g., a symmetric multiprocessor) in a manner that avoids, or at least limits, inefficiencies such as renumbering of node IDs, system reboots, SW configuration handle changes, and the like. In one arrangement, a number of modules, tables and/or the like that are configured to generate node IDs and/or convert node IDs from one form to another form can be intelligently implemented within an SMP to allow the various processes and/or components of an SMP to utilize the node IDs in a more efficient manner. For instance, as SDs in an SMP are often configured to work with CNIDs (e.g., for use in determining at which node a particular requested cache line resides), any node GNIDs that are sent to the SD for processing can first be converted into corresponding CNIDs.

2014004, Feb 6, 2014

Jul 31, 2012

13/563586

Bruce J. Chang - Saratoga CA, US
Sebastian Turullols - Los Altos CA, US
Brian F. Keish - San Jose CA, US
Damien Walker - San Jose CA, US
Ramaswamy Sivaramakrishnan - San Jose CA, US
Paul N. Loewenstein - Palo Alto CA, US

G06F 13/38

710316

Systems and methods for efficient data transport across multiple processors when link utilization is congested. In a multi-node system, each of the nodes measures a congestion level for each of the one or more links connected to it. A source node indicates when each of one or more links to a destination node is congested or each non-congested link is unable to send a particular packet type. In response, the source node sets an indication that it is a candidate for seeking a data forwarding path to send a packet of the particular packet type to the destination node. The source node uses measured congestion levels received from other nodes to search for one or more intermediate nodes. An intermediate node in a data forwarding path has non-congested links for data transport. The source node reroutes data to the destination node through the data forwarding path.

2014005, Feb 27, 2014

Aug 27, 2012

13/595338

Bruce J. Chang - Saratoga CA, US

H04L 27/00

375259, 375316

A mechanism for dynamic skew correction in a multi-lane communication link includes a receiver unit including, for each of the lanes, a first-in first-out (FIFO). The FIFO may store received symbols to locations pointed to by a write pointer and output to downstream logic, symbols stored at locations pointed to by a read pointer. The receiver may also include a symbol drop unit that disables the write pointer in response to receiving a start alignment symbol, and enables the write pointer in response to receiving an end alignment symbol. The receiver also includes an alignment unit that disables the read pointer in response to detecting that the end symbol has been received at least one lane but not all lanes. In addition, the alignment unit may enable the read pointer in response to a determination that the end symbol has been received on all lanes.

7487327, Feb 3, 2009

Jun 1, 2005

11/144117

Bruce J. Chang - Saratoga CA, US
Ricky C. Hetherington - Pleasanton CA, US
Brian J. McGee - San Jose CA, US
David M. Kahn - Makawao HI, US
Ashley N. Saulsbury - Los Gatos CA, US

Sun Microsystems, Inc. - Santa Clara CA

G06F 12/00

711203, 710 3, 711154

A processor employing device-specific memory address translation. In one embodiment, a processor may include a device interface configured to receive a memory access request from an input/output (I/O) device, where the request specifies a virtual memory address and a first requestor identifier (ID) that identifies the I/O device. The processor may also include an I/O memory management unit coupled to the device interface and configured to determine whether a virtual-to-physical memory address translation corresponding to the virtual memory address is stored within an I/O memory translation buffer. The I/O memory management unit may be further configured to determine whether a second requestor ID stored within the I/O memory translation buffer and corresponding to the memory address translation matches the first requestor ID. If the first and second requestor IDs do not match, the I/O memory management unit may disallow the memory access request and to signal an error condition.