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Bruce A Christenson, 4915050 SW Patricia Ave, Beaverton, OR 97123

Known as:
Bruce Alan Christenson Bruce A Christianson Bruce Christenson Living Bru Christenson Brucealan Christenson Bruce Christensen
Related to:
Maureen A Hooten 63

Bruce Christenson Phones & Addresses

15050 SW Patricia Ave, Hillsboro, OR 97123    541-4088490   

Hubbard, OR   

Midway, UT   

Forest Grove, OR   

Wilsonville, OR   

Park City, UT   

Mc Farland, WI   

15050 SW Patricia Ave, Hillsboro, OR 97123   

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Bruce Christenson resumes & CV records

Resumes

Bruce Christenson Photo 18

Principal Engineer - Computer Architect

Location:
15050 southwest Patricia Ave, Hillsboro, OR 97123
Industry:
Semiconductors
Work:
Intel Corporation
Principal Engineer - Computer Architect Intel Corporation
Computer Architect Intel Corporation Jan 1997 - Sep 1997
Intern University of Wisconsin-Madison Oct 1996 - Jan 1997
Java Applet Developer State of Wisconsin Jun 1996 - Sep 1996
Intern
Education:
Oregon Health & Science University 2008 - 2010
Master of Science, Masters Oregon Health & Science University 1998 - 2001
Master of Science, Masters, Computer Science University of Wisconsin - Madison 1993 - 1998
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Computer Architecture, Simulations, Processors, Debugging, Verilog, Performance Analysis, Microprocessors, C++, Python, Linux, High Performance Computing, Microarchitecture, Intel, Semiconductors, Perl, Memory, Servers, Server Architecture, Soc, System on A Chip, Dram, Management, Cache Coherency, Technical Writing, Interconnects, Interviewing Skills, Analysis
Interests:
Guitar
Writing
Dog Agility
Scotch
Education
Reading
Science and Technology
Music
Audio Recording
Health
Animal Welfare
Video
Video Games
Languages:
English
Bruce Christenson Photo 19

Bruce Christenson

Bruce Christenson Photo 20

Bruce Christenson

Bruce Christenson Photo 21

Bruce Christenson

Publications & IP owners

Us Patents

Read-Write Switching Method For A Memory Controller

US Patent:
7093059, Aug 15, 2006
Filed:
Dec 31, 2002
Appl. No.:
10/335485
Inventors:
Bruce A. Christenson - Forest Grove OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/02
G11C 8/12
US Classification:
711 5, 711157, 711167, 711169
Abstract:
A system includes a memory device. The memory device has a first bank and a second bank. A memory controller has a write request queue to store write requests. When a read bank conflict exists between a first read request to the first bank and a second read request to the first bank, a first write request is executed to the second bank during a delay. The delay takes place after the first read request is executed and before the second read request is executed.

Fully Buffered Dimm Read Data Substitution For Write Acknowledgement

US Patent:
7444479, Oct 28, 2008
Filed:
Dec 28, 2005
Appl. No.:
11/321322
Inventors:
James W. Alexander - Aloha OR, US
Rajat Agarwal - Beaverton OR, US
Bruce A. Christenson - Forest Grove OR, US
Kai Cheng - Portland OR, US
International Classification:
G06F 12/16
US Classification:
711154, 711168
Abstract:
A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue.

Systems With Variable Link Widths Based On Estimated Activity Levels

US Patent:
7694060, Apr 6, 2010
Filed:
Jun 17, 2005
Appl. No.:
11/155857
Inventors:
James A. McCall - Beaverton OR, US
Bruce A. Christenson - Forest Grove OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/00
US Classification:
710307, 710305, 710105, 710106
Abstract:
In some embodiments, a chip includes transmitters and receivers, and control circuitry. The control circuitry to cause some of the transmitters and receivers to be inoperative in response to an estimated activity level being in a first range, while others of the transmitters and receivers remain operative. Other embodiments are described and/or claimed.

Fully Buffered Dimm Read Data Substitution For Write Acknowledgement

US Patent:
7941618, May 10, 2011
Filed:
Aug 29, 2008
Appl. No.:
12/202088
Inventors:
James W. Alexander - Aloha OR, US
Rajat Agarwal - Beaverton OR, US
Bruce A. Christenson - Forest Grove OR, US
Kai Cheng - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/16
US Classification:
711154, 711167, 711E1204
Abstract:
A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue.

Memory Controller Using Time-Staggered Lockstep Sub-Channels With Buffered Memory

US Patent:
8060692, Nov 15, 2011
Filed:
Jun 27, 2008
Appl. No.:
12/163672
Inventors:
Bruce A. Christenson - Forest Grove OR, US
Rajat Agarwal - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/00
US Classification:
711105, 711 5, 711157
Abstract:
Memory control techniques for dual channel lockstep configurations are disclosed. In accordance with one example embodiment, a memory controller issues two burst-length 4 DRAM commands to two double-data-rate (DDR) DRAM sub-channels behind a memory buffer (e. g. , FB-DIMM or buffer-on-board). The two commands are in time-staggered lockstep. The time-stagger allows data coming back from the two back-side DDR sub-channels to flow naturally on the host channel without conflict. Multiple DIMMs can be used to obtain chip-fail ECC capabilities and to reclaim at least some of the lost performance imposed by the burst-length of 4 s typically associated with dual channel lockstep memory controllers. The techniques can be implemented, for instance, with a buffered memory solution such as fully buffered DIMM (FB-DIMM) or buffer-on-board configurations.

Memory Controller Transaction Scheduling Algorithm Using Variable And Uniform Latency

US Patent:
2006002, Feb 2, 2006
Filed:
Jul 30, 2004
Appl. No.:
10/909084
Inventors:
Bruce Christenson - Forest Grove OR, US
Chitra Natarajan - Flushing NY, US
International Classification:
G06F 13/28
G06F 12/00
US Classification:
711167000, 711158000
Abstract:
A memory method may select a latency mode, such as read latency mode, based on measuring memory channel utilization. Memory channel utilization, for example, may include measurements in a memory controller queue structure. Other embodiments are described and claimed.

Method, System, And Apparatus For Memory Controller Utilization Of An Amb Write Fifo To Improve Fbd Memory Channel Efficiency

US Patent:
2006020, Sep 7, 2006
Filed:
Mar 3, 2005
Appl. No.:
11/073285
Inventors:
Bruce Christenson - Forest Grove OR, US
Chitra Natarajan - Flushing NY, US
International Classification:
G06F 3/00
US Classification:
710057000
Abstract:
A memory controller to support fully buffered DIMMS by utilizing a write FIFO to switch from the default condition of a memory controller scheduling read requests out-of-order to scheduling write transactions from a write FIFO buffer for a predetermined set of conditions is discussed. For example, the predetermined set of conditions are a write buffer structure has exceeded a threshold (wherein the threshold is fixed or specified by a configuration register) and a memory controller has posted a predetermined number of writes to an AMB write FIFO structure (the predetermined number can be fixed or specified by a configuration register).

Method, Apparatus And System To Manage Implicit Pre-Charge Command Signaling

US Patent:
2017014, May 18, 2017
Filed:
Nov 23, 2016
Appl. No.:
15/360675
Inventors:
- Santa Clara CA, US
Bruce A. Christenson - Forest Grove OR, US
Kuljit S. Bains - Olympia WA, US
International Classification:
G11C 7/10
G06F 13/16
Abstract:
Techniques and mechanisms for exchanging information between a memory controller and a memory device. In an embodiment, a memory controller receives information indicating for a memory device a threshold number of pending consolidated activation commands to access that memory device. The threshold number indicated by the information is less than a theoretical maximum number of pending consolidated activation commands, the theoretical maximum number defined based on timing parameters of the memory device. In another embodiment, the memory controller limits communication of consolidated activation commands to the memory device based on the information indicating the threshold number.

Isbn (Books And Publications)

Public School Districts In The United States: A Statistical Profile, 1987-88 To 1993-94

Author:
Bruce Christenson
ISBN #:
0160494206

Possible Relatives

David R Christenson  Dallis J Christenson  Deborah Christenson  Dana E Christenson  Debra L Christenson  Daniel C Christenson  Dee A Christenson  Bruce A Johnson  Bruce K Stamps  Bruce W Johnston 

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