Carlos M Greaves, 3320 Park View Ter, Malden, MA 02148

7135934, Nov 14, 2006

Mar 1, 2005

11/069664

Hector Sanchez - Cedar Park TX, US
Carlos A. Greaves - Austin TX, US
Jim P. Nissen - Austin TX, US
Xinghai Tang - Cedar Park TX, US

Freescale, Semiconductor, Inc. - Austin TX

H03L 7/089
H03L 7/099

331 18, 331 17, 331 57, 331179

A programmable PLL including a receiver, a phase frequency detector, a charge pump, and a VCO. The receiver includes a programmable capacitor voltage divider that shifts voltage of an input clock to provide a level-shifted clock. The AC interface includes a state detection and correction circuit that ensures proper state of the level-shifted clock. The PLL includes a pulse delay modulator for generating delayed clock control signals. The VCO includes a programmable phase control circuit that dynamically adjusts phase using the delayed clock control signals. The VCO circuit includes a ring oscillator circuit with one or more phase control nodes. The programmable phase control circuit selectively couples devices to the phase control node using the clock control signals to adjust phase. The devices may be capacitors or transistors, each switched using switches controlled by the delayed clock control signals. The capacitors may be metal capacitors or semiconductor transistor capacitors.

7183817, Feb 27, 2007

Jun 29, 2005

11/169862

Hector Sanchez - Cedar Park TX, US
Xinghai Tang - Cedar Park TX, US
Carlos A. Greaves - Austin TX, US
Jim P. Nissen - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H03K 3/00

327112, 327333

A high speed output buffer including an input circuit providing first and second signals within a first voltage range having a first common mode voltage, an AC interface receiving the first and second signals and providing first and second preliminary drive signals, a detection and correction circuit that corrects a state of the first preliminary drive signal AC coupled to the first signal, first and second drive circuits receiving the preliminary drive signals and providing first and second drive signals, where the first drive circuit operates within a second voltage range having a greater common mode voltage and where the second drive circuit operates within a third voltage range, and an output that switches an output node within a voltage range that is greater than a maximum voltage range. The first, second and third voltage ranges are each within the maximum voltage range suitable for thin-gate devices.

7221613, May 22, 2007

May 26, 2004

10/854554

Perry H. Pelley - Austin TX, US
Carlos A. Greaves - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G11C 8/00

36523003, 36523008, 365233

A memory () has a plurality of memory cells, a transceiver () for receiving a low voltage high frequency differential address signal, and a serial input/output data port () for receiving a high frequency low voltage differential data signal. The memory () can operate in one of two different modes, a normal mode and a cache line mode. In cache line mode, the memory can access an entire cache line from a single address. A fully hidden refresh mode allows for timely refresh operations while operating in cache line mode. Data is scored in the memory array () by interleaving in multiple sub-arrays (). During a hidden refresh mode of operation, one sub-array () is accessed while another sub-array () is refreshed. Two or more of the memories () may be chained together to provide a high speed low power memory system.

7240041, Jul 3, 2007

Nov 25, 2003

10/721196

Harold M. Martin - Austin TX, US
Carlos A. Greaves - Austin TX, US
Thang Q. Nguyen - Austin TX, US
Jose M. Nunez - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G06F 17/00
G06N 5/02

706 48

Hashing and pattern matching are used in an information processing system to process incoming messages from a network such as an Ethernet-based network. Using hashing and pattern matching increases the efficiency of message acceptance and rejection without increasing software-based processor tasks. A hash function and a pattern matching function are performed on a message received by an information processing system, and the message is selectively accepted based on at least one of a hash result and a pattern matching result. The incoming message can be searched for the existence of patterns and the absence of the patterns. The incoming message can be searched for the existence of multiple patterns. The results of pattern matching can be used not only for acceptance and rejection of messages, but also for other post-receipt tasks such as selective storage of incoming messages according to identified relative priorities or absolute criticality of messages having particular pattern matches.

7474585, Jan 6, 2009

Apr 17, 2007

11/736231

Perry H. Pelly - Austin TX, US
Carlos A. Greaves - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G11C 8/00

36523003, 36523008, 365233

A memory () has a plurality of memory cells, a serial address port () for receiving a low voltage high frequency differential address signal, and a serial input/output data port () for receiving a high frequency low voltage differential data signal. The memory () can operate in one of two different modes, a normal mode and a cache line mode. In cache line mode, the memory can access an entire cache line from a single address. A fully hidden refresh mode allows for timely refresh operations while operating in cache line mode. Data is stored in the memory array () by interleaving in multiple sub-arrays (). During a hidden refresh mode of operation, one sub-array () is accessed while another sub-array () is refreshed. Two or more of the memories () may be chained together to provide a high speed low power memory system.

7613775, Nov 3, 2009

Nov 25, 2003

10/721201

Carlos A. Greaves - Austin TX, US
Harold M. Martin - Austin TX, US
Thang Q. Nguyen - Austin TX, US
Jose M. Nunez - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G06F 15/16
G06N 5/02

709206, 709250, 706 48

Hashing and pattern matching are used in an information processing system to process incoming messages from a network such as an Ethernet-based network. Using hashing and pattern matching increases the efficiency of message acceptance and rejection without increasing software-based processor tasks. A hash function and a pattern matching function are performed on a message received by an information processing system, and the message is selectively accepted based on at least one of a hash result and a pattern matching result. The incoming message can be searched for the existence of patterns and the absence of the patterns. The incoming message can be searched for the existence of multiple patterns. The results of pattern matching can be used not only for acceptance and rejection of messages, but also for other post-receipt tasks such as selective storage of incoming messages according to identified relative priorities or absolute criticality of messages having particular pattern matches.

7859299, Dec 28, 2010

Jul 10, 2009

12/500975

James G. Gay - Pflugerville TX, US
Carlos A. Greaves - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H03K 17/16
G11C 7/10

326 30, 326 62, 36518906

A method and circuit includes providing at least one conductor for receiving an input signal. A termination circuit and a clamp circuit are coupled to the at least one conductor. The termination circuit is enabled while the clamp circuit remains enabled. The clamp circuit is disabled. After disabling the clamp circuit, while the termination circuit remains enabled, both a first differential comparator and a second differential comparator are enabled. The first differential comparator receives a first differential input signal at a first input and a second differential input signal at a second input. The second differential comparator detects when a difference between the first differential input signal and the second differential input signal is greater than a predetermined value and enables transfer of an output of the first differential comparator to a memory controller.

7268588, Sep 11, 2007

Jun 29, 2005

11/170398

Hector Sanchez - Cedar Park TX, US
Carlos A. Greaves - Austin TX, US
Jim P. Nissen - Austin TX, US
Xinghai Tang - Cedar Park TX, US

Freescale Semiconductor, Inc. - Austin TX

H03K 19/094

326 68, 326 81, 326 86

A level shifter circuit including first and second circuits and a protection layer. The first circuit receives an input signal and switches first and second nodes to opposite states within a first voltage range between first and second supply voltages. The second circuit switches the third and fourth nodes to opposite states within a second voltage range between third and fourth supply voltages in response to switching of the first and second nodes. The protection layer couples the first and second nodes to third and fourth nodes via respective first and second isolation paths. The isolation paths operate to keep the first and second nodes within the first voltage range and to keep the third and fourth nodes within the second voltage range. Isolation enables the use of thin gate-oxide devices for speed while extending the voltage range beyond the maximum voltage allowable for a single thin gate-oxide device.