Caroline D Benveniste, 63125 12Th St, New York, NY 10011

6353871, Mar 5, 2002

Feb 22, 1999

09/256572

Caroline D. Benveniste - New York NY
Peter A. Franaszek - Mount Kisco NY
John T. Robinson - Yorktown Heights NY
Charles O. Schulz - Ridgefield CT

International Business Machines Corporation - Armonk NY

G06F 1208

711 3, 711118

A system including a CPU, memory, and compression controller hardware, and implementing a first directory structure included in a first memory wherein CPU generated real memory addresses are translated into one or more physical memory locations using the first directory structure, further includes a second directory cache structure having entries corresponding to directory entries included in the first directory structure. In a first embodiment, the second directory cache structure is implemented as part of compression controller hardware. In a second embodiment, a common directory and cache memory structure is provided for storing a subset of directory entries in the directory structure together with a subset of the memory contents.

6587923, Jul 1, 2003

May 22, 2000

09/575549

Caroline D. Benveniste - New York NY
Peter A. Franaszek - Kisco NY
John T. Robinson - Yorktown Heights NY

International Business Machines Corporation - Armonk NY

G06F 1206

711122, 711144, 711128

In a computer system having a processor, a memory system including multiple levels of caches L , L ,. . . , L and including main memory L , and in which the cache L includes lines of size s and the cache L includes lines of size t with t s, a dual line size cache directory mechanism, in which the contents of a cache L may be accessed at line size granularity s (in which case it is determined whether a line corresponding to a given memory address is stored in L , and if so its location and status), and in which the contents of L may also be accessed at line size granularity t (in which case it is determined whether any of the t/s lines of size s residing in the larger line of size t corresponding to a given memory address are stored in L , and if so their locations and status) without multiple sequential accesses to a cache L directory structure.

6779088, Aug 17, 2004

Oct 24, 2000

09/694876

Caroline D. Benveniste - New York NY
Peter A. Franaszek - Mt. Kisco NY
John T. Robinson - Yorktown Heights NY

International Business Machines Corporation - Armonk NY

G06F 1208

711145, 711144, 711156, 711170, 709247, 710 68

A compressed memory system includes a cache, and compressed memory including fixed size storage blocks for storing both compressed data segments and fixed size storage blocks defining a virtual uncompressed cache (VUC) for storing uncompressed data segments to enable reduced data access latency. The compressed memory system implements a system and method for controlling the size of the VUC so as to optimize system performance in a manner which permits the avoidance of operating system intervention which is required in certain circumstances for correct system operation. The system solves-these problems by implementing one or more thresholds, which may be set by the operating system, but which, after being sets control the size of the VUC independently of the operating system or other system software.

6795897, Sep 21, 2004

May 15, 2002

10/146692

Caroline Benveniste - New York NY
Vittorio Castelli - Croton-on-Hudson NY
Peter A. Franaszek - Mount Kisko NY

International Business Machines Corporation - Armonk NY

G06F 1200

711118, 711202, 707101, 710 68

A computer system and corresponding method for supporting a compressed main memory includes a processor, a processor cache in signal communication with the processor, a memory controller in signal communication with the processor cache, a compression translation table entry register in signal communication with the processor cache and the memory controller, a compression translation table directory in signal communication with the compression translation table entry register, and a compressed main memory in signal communication with the memory controller wherein the memory controller manages the compressed main memory by storing entries of the compression translation table directory into the processor cache from the compression translation table entry register; where the corresponding method includes receiving a real address for a processor cache miss, finding a compression translation table address for the cache miss within the processor cache, if the cache miss is a cache write miss: decompressing the memory line corresponding to the cache line being written, writing the content of the cache line into the appropriate position in the memory line, compressing the data contained in said memory line, and storing the compressed data into the compressed main memory, and, if the cache miss is a cache read miss: retrieving the compressed data corresponding to the compression translation table address from the compressed main memory and decompressing the retrieved data.

7103722, Sep 5, 2006

Jul 22, 2002

10/200937

Caroline Benveniste - New York NY, US
Peter Franaszek - Mt. Kisco NY, US
John T. Robinson - Yorktown Heights NY, US
Charles Schulz - Ridgefield CT, US

International Business Machines Corporation - Armonk NY

G06F 12/00

711134, 711133, 711136, 711129, 711118, 711120, 711142, 714 5, 714 42

A method and structure is disclosed for constraining cache line replacement that processes a cache miss in a computer system. The invention contains a K-way set associative cache that selects lines in the cache for replacement. The invention constrains the selecting process so that only a predetermined subset of each set of cache lines is selected for replacement. The subset has at least a single cache line and the set size is at least two cache lines. The invention may further select between at least two cache lines based upon which of the cache lines was accessed least recently. A selective enablement of the constraining process is based on a free space memory condition of a memory associated with the cache memory. The invention may further constrain cache line replacement based upon whether the cache miss is from a non-local node in a nonuniform-memory-access system. The invention may also process cache writes so that a predetermined subset of each set is known to be in an unmodified state.

7958289, Jun 7, 2011

Aug 8, 2002

10/214171

Caroline Benveniste - New York NY, US
Vittorio Castelli - Croton-on-Hudson NY, US
Peter A. Franaszek - Mt. Kisco NY, US

International Business Machines Corporation - Armonk NY

G06F 13/38
G06F 13/00

710 68, 711111, 711168

A method (and system) of storing information, includes storing main memory compressed information onto a memory compressed disk, where pages are stored and retrieved individually, without decompressing the main memory compressed information.

7979602, Jul 12, 2011

Aug 20, 2009

12/544513

Caroline Benveniste - New York NY, US
Vittorio Castelli - Croton-on-Hudson NY, US
Peter A. Franaszek - Mt. Kisco NY, US

International Business Machines Corporation - Armonk NY

G06F 13/38
G06F 13/00

710 33, 711111, 711168, 710 22, 710 68

A method (and system) of storing information, includes storing main memory compressed information onto a memory compressed disk, where pages are stored and retrieved individually, without decompressing the main memory compressed information.

8161206, Apr 17, 2012

Apr 8, 2011

13/083400

Caroline Benveniste - New York NY, US
Vittorio Castelli - Croton-on-Hudson NY, US
Peter A. Franaszek - Mt. Kisco NY, US

International Business Machines Corporation - Armonk NY

G06F 13/38
G06F 13/00

710 33, 711111, 711168, 710 22, 710 68

In a computer system supporting memory compression and wherein data is stored on a disk in a different compressed format, and wherein an IOA (input/output adaptor)/IOP (input/output processor) selectively reads from and writes to a main memory through a direct memory access (DMA) operation, a method for transmitting compressed data from the IOA/IOP to the main memory includes reserving a set of free memory sectors to contain the data in said main memory, sending to the IOA/IOP addresses of said memory sectors, copying the data from the IOA/IOP to said memory sectors using said DMA operation, constructing at the IOA/IOP compressed memory directory information defining how and where the data is stored in memory, sending the memory directory information to a memory controller, and storing the memory directory information in the compressed memory directory structure.