Cathy S May, 77184 Ascan Ave, Forest Hills, NY 11375

6823445, Nov 23, 2004

Jul 31, 2001

09/918813

Cathy May - Millwood NY
Edward John Silha - Austin TX

International Business Machines Corporation - Armonk NY

G06F 944

712226, 717111, 717168

A method, program, and system for modifying computer program instructions during execution of those instructions are provided. The invention comprises writing a first instruction into a memory location, wherein the instruction is a patch class instruction. This first instruction is then fetched from the memory location and executed. Concurrent with execution of the first instruction, the memory location is overwritten with a second instruction, which is also a patch class instruction. Because the first and second instructions are patch class instructions, if a program is executing from the memory location, or returns to execute from that location, it will fetch and execute either the first instruction or the second instruction. In one embodiment, reconciling the processors execution pipeline with the memory location will ensure that the second instruction is fetched and executed if the program returns to execute from that location.

2021009, Apr 1, 2021

Sep 30, 2019

16/588380

- Armonk NY, US
BENJAMIN HERRENSCHMIDT - Lyneham, AU
CATHY MAY - Ossining NY, US
BRADLY G. FREY - AUSTIN TX, US

G06F 9/30
G06F 12/1009
G06F 12/1027

A processor core processes a translation load instruction including a protection field specifying a desired access protection to be specified in a translation entry for a memory page. Processing the translation load instruction includes calculating an effective address within the memory page and ensuring that a translation entry containing the desired access protection is stored within at least one translation structure of the data processing system.

2020020, Jun 25, 2020

Dec 19, 2018

16/225803

- Armonk NY, US
BENJAMIN HERRENSCHMIDT - LYNEHAM, AU
CATHY MAY - OSSINING NY, US
BRADLY G. FREY - AUSTIN TX, US

G06F 12/1027
G06F 12/0815
G06F 9/52
G06F 12/0842
G06F 9/38
G06F 9/30
G06F 9/48

A processor core among the plurality of processor cores initiates invalidation of translation entries buffered in the plurality of processor cores by executing a translation invalidation instruction in an initiating hardware thread. The processor core also executes, in the initiating hardware thread, a synchronization instruction following the translation invalidation instruction in program order that determines completion of invalidation, at all of the plurality of processor cores, of the translation entries specified by the translation invalidation instruction and draining of any memory referent instructions whose target addresses have been translated by reference to the translation entries. A register is updated to a state based on a result of the determination. The processor core branches execution to re-execute the synchronization instruction based on the state of the register indicating that the translation entries are not invalidated at all of the plurality of processor cores.