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Cecil Kent Walters, 816407 83Rd St, Scottsdale, AZ 85250

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Us Patents

Pin Or Nip Low Capacitance Transient Voltage Suppressors And Steering Diodes

US Patent:
7009831, Mar 7, 2006
Filed:
Feb 27, 2004
Appl. No.:
10/788536
Inventors:
Cecil Kent Walters - Scottsdale AZ, US
Assignee:
Microsemi Corporation - Irving CA
International Classification:
H02H 3/22
H01L 31/075
US Classification:
361111, 361119, 257656
Abstract:
Unidirectional and bi-directional low capacitance transient voltage suppressors (“TVS”) and steering diodes are disclosed. In one embodiment, the TVS comprise TVS p-n junction diode element(s), () low-capacitance (“LC”) PIN or NIP diode element(s) (), the TVS p-n junction diode element(s) () being placed in series with and in opposite polarity to the LC PIN or NIP diodes (). In another embodiment, the steering diode comprise only LC PIN or NIP diode(s) () arranged as steering diodes.

Uni-Directional Pin Or Nip Conducting Low Capacitance Transient Voltage Suppressors And Steering Diodes

US Patent:
7084486, Aug 1, 2006
Filed:
Mar 3, 2005
Appl. No.:
11/071128
Inventors:
Cecil Kent Walters - Scottsdale AZ, US
Assignee:
Microsemi Corporation - Irvine CA
International Classification:
H01L 31/075
H02M 3/335
H02H 3/22
US Classification:
257656, 363 20, 361111, 361119
Abstract:
A device for protecting I/O lines using PIN or NIP low capacitance transient voltage suppressors and steering diodes are disclosed. In an exemplary embodiment, a two (2) terminal device with a unidirectional low capacitance TVS diode () and an anti-parallel LC PIN or NIP diode () is disclosed. To provide for a low capacitance TVS with a forward conducting low-voltage characteristic, the LC PIN or NIP diode is placed anti-parallel to the unidirectional low capacitance TVS. This LC PIN or NIP diode must also have a reverse blocking voltage greater than the avalanche breakdown p-n junction voltage (V) of the unidirectional TVS.

Bi-Directional Pin Or Nip Low Capacitance Transient Voltage Suppressors And Steering Diodes

US Patent:
7164568, Jan 16, 2007
Filed:
Mar 3, 2005
Appl. No.:
11/071513
Inventors:
Cecil Kent Walters - Scottsdale AZ, US
Assignee:
Microsemi Corporation - Irvine CA
International Classification:
H02H 3/22
US Classification:
361111, 363 20, 257656
Abstract:
A bi-directional low capacitance TVS using a PIN or NIP diode is disclosed. Bi-directional low capacitance TVS protection circuit () consists of two pairs of TVS diodes (), () and LC PIN or NIP diodes (), (). Diodes () and () are in parallel and in opposite direction from a first series of TVS and LC diode pair. This circuit provides transient protection in both directions for a bi-directional low capacitance TVS.

Device For Protecting I/O Lines Using Pin Or Nip Conducting Low Capacitance Transient Voltage Suppressors And Steering Diodes

US Patent:
7187012, Mar 6, 2007
Filed:
Mar 3, 2005
Appl. No.:
11/071127
Inventors:
Cecil Kent Walters - Scottsdale AZ, US
Assignee:
Microsemi Corporation - Irvine CA
International Classification:
H01L 29/00
US Classification:
257106, 257601, 361111
Abstract:
A device for protecting I/O lines using low capacitance steering diodes () and PIN or NIP diodes (), () is disclosed. A low capacitance diode arrangement configured as steering diodes protect a signal line or input/output (I/O) port () from high voltage transients by diverting or directing the transient to either the positive side of the power supply line () or to ground ().

Surface Mountable Diode

US Patent:
4709253, Nov 24, 1987
Filed:
May 2, 1986
Appl. No.:
6/859126
Inventors:
Cecil K. Walters - Scottsdale AZ
Assignee:
AMP Incorporated - Harrisburg PA
International Classification:
H01L 2348
US Classification:
357 68
Abstract:
A surface mountable bipolar zener diode includes first and second semiconductor elements, each of which defines a respective p-n junction near a respective inner face, and each of which defines a respective metallized layer on a respective outer face. The inner faces are soldered together such that the p-n junctions are disposed near the center of the assembled diode. The outer faces are operated parallel to one another and to the p-n junctions and are disposed perpendicularly to a pair of printed circuit board contacts. Fillets of solder or conductive epoxy extend between the metallized layers and the printed circuit board contacts to interconnect the bipolar zener diode with the printed circuit board contacts.

Method And Apparatus For Zero Temperature Coefficient Reference Voltage Devices

US Patent:
5164615, Nov 17, 1992
Filed:
Jun 3, 1991
Appl. No.:
7/709320
Inventors:
Cecil K. Walters - Scottsdale AZ
Assignee:
Microsemi Corp. - Scottsdale AZ
International Classification:
H03K 326
H03K 1908
US Classification:
3073172
Abstract:
A reference voltage device that consists of a series combination of reverse biased p-n junctions, forward biased p-n junctions, and Schottky hot carrier diodes. The relatively low voltage and low negative temperature coefficient of Schottky diodes permit great flexibility in correcting areas of nonlinearity in the offsetting temperature dependent characteristics of conventional forward biased junctions and zener diodes. Because of the stability of Schottky hot carrier diodes to radiation, the method and apparatus of this invention are particularly suitable for designing radiation hardened reference diodes, as well. Finally, the Schottky forward biased diode is suitable for integration into a single monolithic chip structure in series with conventional reverse and forward biased p-n junctions.

Sic Transient Voltage Suppressor

US Patent:
2016012, May 5, 2016
Filed:
Feb 13, 2015
Appl. No.:
14/622309
Inventors:
- Bend OR, US
Bruce Odekirk - Bend OR, US
Cecil Kent Walters - Scottsdale AZ, US
International Classification:
H01L 29/06
H01L 29/16
H01L 29/36
H01L 29/872
Abstract:
A high power, high current Unidirectional Transient Voltage Suppressor, formed on SiC starting material is disclosed. The device is structured to avalanche uniformly across the entire central part (active area) such that very high currents can flow while the device is reversely biased. Forcing the device to avalanche uniformly across designated areas is achieved in different ways but consistently in concept, by creating high electric fields where the device is supposed to avalanche (namely the to active area) and by relaxing the electric field across the edge of the structure (namely in the termination), which in all embodiments meets the conditions for an increased reliability under harsh environments.

Voidlessly Encapsulated Semiconductor Die Package

US Patent:
2014031, Oct 30, 2014
Filed:
Apr 22, 2014
Appl. No.:
14/258775
Inventors:
- Aliso Viejo CA, US
Cecil Kent Walters - Scottsdale AZ, US
Assignee:
MICROSEMI CORPORATION - Aliso Viejo CA
International Classification:
H01L 23/31
H01L 23/00
H01L 29/16
US Classification:
257 77, 438127
Abstract:
A system can include a semiconductor die having a first side and a second side opposite the first side. The system can also include a first slug coupled to a portion of the first side of the die. The system can further include a second slug coupled to a portion of the second side of the die. The system can additionally include an insulating material voidlessly encapsulating the die. The first slug can include a first portion having a first width in proximity to the die and a second portion having a second width. The first portion can be closer than the second portion to the die and the first width can be smaller than the second width.

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