Chang H Choi, 57San Jose, CA

6759339, Jul 6, 2004

Dec 13, 2002

10/319318

Chang Ju Choi - Fremont CA
Benjamin Schwarz - Santa Clara CA

Silicon Magnetic Systems - San Jose CA

H01L 21302

438710, 438714

A method is provided which includes pulsing power applied to a microelectronic topography between a high level and a low level during a plasma etch process. In particular, the high level may be sufficient to form etch byproducts at a faster rate than a rate of removal of the etch byproducts from the reaction chamber at the high level. In contrast, the low level may be sufficient to form etch byproducts at a rate that is less than a rate of removal of the etch byproducts at the low level. In this manner, an etched topography may be formed without an accumulation of residue upon its periphery. Such a method may be particularly beneficial in an embodiment in which the etch byproducts include a plurality of nonvolatile compounds, such as in the fabrication of a magnetic junction of an MRAM device, for example.

7205164, Apr 17, 2007

Jan 19, 2005

11/039301

Sam Geha - Cupertino CA, US
Benjamin C. E. Schwarz - San Jose CA, US
Chang Ju Choi - Fremont CA, US
Biju Parameshwaran - Union City CA, US
Eugene Y. Chen - Fremont CA, US
Helen L. Chung - San Jose CA, US
Kamel Ounadjela - Belmont CA, US
Witold Kula - Cupertino CA, US

Silicon Magnetic Systems - San Jose CA

H01L 21/00

438 3, 438240, 257E21665

Methods for patterning a magnetic cell junction and a topography used for and/or resulting from such methods are provided. In particular, a method is provided which includes etching portions of a topography adjacent to a patterned photoresist layer to a level within a cap film of the topography, removing etch residues from the topography and subsequently etching the remaining portions of the cap film to expose an uppermost magnetic layer. Another method is provided which includes patterning a dielectric mask layer above a patterned upper portion of a magnetic cell junction and ion milling a lower portion of the magnetic cell junction in alignment with the mask layer. An exemplary topography which may result and/or may be used for such methods includes a stack of layers having a dual layer cap film arranged above at least two magnetic layers spaced apart by a tunneling layer.

8399158, Mar 19, 2013

Dec 23, 2010

12/977903

Chang Ju Choi - Fremont CA, US
Cheng-Hsin Ma - Redwood City CA, US
Sven Henrichs - San Jose CA, US
Robert H. Olshausen - Menlo Park CA, US
Yulia Korobko - Saratoga CA, US

Intel Corporation - Santa Clara CA

G03F 1/26

430 5

Techniques are disclosed for fabricating lithography masks, which include a first level process comprising lithography and etching to form mask frame and in-die areas, and a second level process comprising lithography and etching to form one or more mask features in the in-die area. At least one of the mask features has a smallest dimension in the nanometer range (e. g. , 32 nm technology node, or smaller). The techniques may be embodied, for example, in a lithography mask for fabricating semiconductor circuits. In one such example case, the mask includes a frame area and an in-die area formed after the frame area. The in-die area includes one or more mask features, at least one of which has a smallest dimension of less than 100 nm. The mask has a critical dimension bias of less than 20 nm and a structure that comprises a substrate and an absorber layer.

2014003, Jan 30, 2014

Jul 30, 2012

13/561410

Chang Ju Choi - Fremont CA, US

G03F 1/26

430 5

Techniques are disclosed for enhancing critical dimension (CD) resolution in photomask processing. In some cases, the techniques can be implemented, for instance, to enhance space and line pattern resolution independently on a given phase-shifting photomask (PSM). The disclosed techniques can be implemented, for example, to extend existing photolithography techniques/technologies (e.g., 193 nm photolithography) to additional process nodes. For instance, some embodiments can be used to produce extremely high-resolution photomasks which generate features having sizes in the 10 nm node and beyond. The disclosed techniques can be implemented in the fabrication of a wide range of integrated circuits (ICs) and other devices.

2023011, Apr 13, 2023

Sep 27, 2022

17/953575

- Santa Clara CA, US
Yang Ming Lee - Singapore, SG
Hsiao-Ying Cheng - Singapore, SG
Christabelle Si Mei Goh - Singapore, SG
Ustun Serdar Tulu - Los Altos CA, US
Chang H. Choi - San Jose CA, US
Chloe Kim - Mountain View CA, US

Applied Materials, Inc. - Santa Clara CA

G01N 1/34
G01N 1/44
G01N 21/64

Exemplary sample processing methods are described that include providing an initial sample to a sample processing system. The sample processing system includes a light-emitting-diode, a temperature control unit, and a fluid supply unit. The methods also include irradiating the initial sample with light emitted from the light-emitting-diode to produce an irradiated sample. The methods may still further include adjusting a temperature of the irradiated sample with the temperature control unit to between 0 C. and 60 C., and contacting the irradiated sample with a fluid from the fluid supply unit. The irradiated sample has a reduction in auto-fluorescence of greater than or about 50% compared to the initial sample. Exemplary sample processing systems are also described that include a light-emitting-diode, a temperature control unit, and a fluid supply unit.

2021031, Oct 7, 2021

Apr 11, 2019

17/046693

- Carlsbad CA, US
Jonathan ZMUDA - Frederick MD, US
Sara BARNES - Germantown MD, US
Chang CHOI - San Diego CA, US
Kenneth THOMPSON - Burtonsville MD, US

C12N 15/86
C12N 5/07
C12N 7/00
C12P 21/00

The present disclosure is related generally to systems and methods for high level expression of recombinant proteins from baculovirus in insect cells. In particular, the methods and systems described herein allow for high levels of baculovirus production in insect cells and/or high levels of protein production in insect cells using a chemically-defined, yeast lysate-free insect cell medium. The disclosure also relates to compositions and kits for culturing, transfecting, and/or producing recombinant protein in insect cells.

2021013, May 6, 2021

Oct 31, 2019

16/670564

- Singapore, SG
Chris Chung - Seoul, KR
Michael Leary - Sunnyvale CA, US
Domingo Figueredo - Jacksonville FL, US
Chang Kyu Choi - Fremont CA, US
Sarah Haney - San Jose CA, US
Li Sun - San Jose CA, US

H01L 23/00
H01L 23/13
H01L 23/498
H01L 21/48

A device and substrate are disclosed. An illustrative device includes a substrate having a first surface and an opposing second surface, a solder material receiving curved surface exposed at the second surface of the substrate, a solder resist material that at least partially covers the solder material receiving curved surface such that a middle portion of the solder receiving curved surface is exposed and such that an edge portion of the solder material receiving curved surface is covered by the solder resist material and forms an undercut, and a solder material disposed within the solder material receiving curved surface and within the undercut.

2020024, Jul 30, 2020

Jan 29, 2019

16/260429

- Singapore, SG
Nitesh Kumbhat - San Jose CA, US
Li Sun - San Jose CA, US
Sarah Haney - San Jose CA, US
Chang Kyu Choi - Fremont CA, US

H05K 1/18
H05K 1/11
H01R 12/57

An electronic device includes a printed circuit board (PCB) defining a cavity, a first component pad of the PCB positioned outside the cavity, and a second component pad of the PCB positioned on a bottom surface of the cavity. The first component pad has a first thickness, and the second component pad has a second thickness that is less than the first thickness of the first component pad. An electronic component, such as a surface mounted technology (SMT) component, is mounted to the second component pad within the cavity.