Position:
Senior Research Scientist at Intel Corporation
Work:
Intel Corporation
- Portland, Oregon Area since Oct 2011
Senior Research Scientist
Purdue University
Aug 2006 - Sep 2011
Graduate Research Assistant
Intel Corporation
May 2010 - Sep 2010
Research Intern
Freescale Semiconductor
May 2008 - Aug 2008
Research Intern
Philips Semiconductors
Jul 2005 - Jul 2006
Design Engineer
Texas Instruments
Jun 2004 - Jul 2005
Design Engineer
ST Microelectronics
Jan 2004 - Jun 2004
Research Intern
Bhabha Atomic Research Centre
May 2002 - Jul 2002
Research Intern
Education:
Purdue University 2006 - 2011
Ph.D., Electrical and Computer Engineering
Birla Institute of Technology and Science 2000 - 2004
BE, Electronics & Instrumentation
Skills:
VLSI, Logic Synthesis, Timing Closure, Embedded Systems, CMOS, Cadence, Computer Architecture, Photolithography, Device Characterization, Cadence Virtuoso, Integrated Circuit Design, Verilog, Circuit Design, ModelSim, Analog Circuit Design
Honor & Awards:
Received "Best Paper in Session Award" at SRC Techcon 2009 for the paper titled “A Comprehensive Nano-magnet Based Logic Synthesis for Ultra-Low Power Digital Systems.”
Received "Best Paper Award" at International Symposium on Low Power Electronic Design (ISLPED) 2012 for the paper titled “ TapeCache: A High Density, Energy Efficient Cache Based on Domain Wall Memory ”.
Our Paper titled "Spin-Transfer Torque MRAMs for Low Power Memories: Perspective and Prospective," is one of the 25 most downloaded Sensors Journal papers in the month of March, 2012.
Nominated for "Best Paper Award" at International Symposium on Quality Electronic Design (ISQED) 2009 for the paper titled “A Device/Circuit Analysis Framework for Evaluation and Comparison of Charge Based Emerging Devices”.
Received "AMD Design Excellence Award" for the Adv. VLSI Design class at Purdue University for the project titled “Complimentary Ferroelectric Capacitor (CFC) Logic: Application to TAG RAM”, 2008.
