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Chen Zhang14485 Roosevelt Ave APT 3C, Flushing, NY 11354

Known as:
Zhong Y Chen Ming Zhang Chen Zhongye Chen Uhang Chen Chen Zhongye
Related to:
Jing Chen Lin L Chen 34 Yinou Chen 35 Zhen Lin Feng 54 Yanyan Chen Yang Chen Chen 47 Wen Chen 60 Won S Chan 75 Zhang Tiechen 53 Ye Chen Zhong 46 Nanxi Zhang Long Chen Guan 80 Zhongming Wang 54 Chang Chen Lida Zhang Hsinmei Chen Chen Zang Xiaoyan Zhang Dan Dan Chen 32 Jun Chen Kong 48

Chen Zhang Phones & Addresses

14485 Roosevelt Ave APT 3C, Flushing, NY 11354   

13642 Maple Ave, Flushing, NY 11355    718-9615348   

Duluth, MN   

Bronx, NY   

Queens, NY   

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Mentions for Chen Zhang

Career records & work history

Lawyers & Attorneys

Chen Zhang Photo 1

Chen Zhang - Lawyer

Address:
212-8939787 (Office)
Licenses:
New York - Currently registered 2007
Education:
University of California Berkeley School of Law
Chen Zhang Photo 2

Chen Zhang - Lawyer

ISLN:
1000783018
Admitted:
2016
Chen Zhang Photo 3

Chen Zhang - Lawyer

Office:
Latham & Watkins LLP
Specialties:
Securities Offerings, Mergers & Acquisitions, Business, Securities Offerings
ISLN:
1000736078
Admitted:
2015
Law School:
University of Texas School of Law, Doctor of Jurisprudence/Juris Doctor (J.D.), 2015
Chen Zhang Photo 4

Chen Zhang - Lawyer

ISLN:
1001052086
Admitted:
2021
Chen Zhang Photo 5

Chen Bin Zhang

Medicine Doctors

Chen Zhang Photo 6

Chen Zhang

Specialties:
Pathology
Clinical Pathology

License Records

Chen Zhang

Licenses:
License #: 065034803 - Active
Issued Date: Jun 12, 2008
Expiration Date: Sep 30, 2018
Type: Licensed Certified Public Accountant
License #: 239018374 - Expired
Issued Date: Mar 24, 2008
Expiration Date: Sep 30, 2009
Type: Registered Certified Public Accountant

Chen Zhang

Licenses:
License #: 06108 - Active
Category: Accountants
Issued Date: Jul 13, 2012
Expiration Date: Jun 30, 2019
Type: Certified Public Accountant

Chen Zhang

Licenses:
License #: 06108 - Active
Category: Accountants
Issued Date: Jul 13, 2012
Expiration Date: Jun 30, 2019
Type: Certified Public Accountant

Chen Zhang resumes & CV records

Resumes

Chen Zhang Photo 54

Chen Zhang - Chicago, IL

Work:
Goldman Sachs - New York, NY Jun 2012 to Aug 2012
Technology Summer Analyst Arbsoft, LLC - Chicago, IL Jun 2011 to May 2012
Financial Software Developer Intern Personal Finance Department, Bank of China - Hohhot Jun 2009 to Aug 2009
Summer Intern China Undergraduate Mathematical Contest in Modeling 2009 to 2009
Tam Leader Mathematical Contest in Modeling in North America 2009 to 2009
Team Leader
Education:
Illinois Institute of Technology, Stuart School of Business - Chicago, IL 2010
Master of Mathematical Finance Beijing Language and Culture University 2006 to 2010
Bachelor of Science in Management Information System
Skills:
Key Skills Proficient with C++, JAVA, C#, VB, .Net 4, VBA, Python, XML, HTML, UML and SQL Strong knowledge in component development, C# assembly, object-oriented design, software engineering Proficient with MS SQLServer, Power Builder, MS Access, Excel, Visio, Project, PowerPoint Familiar with CQGNet, X_Trader, Bloomberg terminal and CTS T4 trading software
Chen Zhang Photo 55

Chen Zhang - San Jose, CA

Work:
NOVOGRADAC & COMPANY LLP Jan 2014 to 2000
Staff Accountant (Temporary) 3x1 NYC, LLC
Bookkeeper GENERAL ELECTRIC
Staff Accountant CHENGDU BANGBANGWA INDUSTRY CO. LTD
Financial Analyst BLOCK CLUBS & NEIGHBORHOOD ASSOCIATIONS - EC, INC
Bookkeeper - Accounting Intern DEPARTMENT OF ACCOUNTING, UNIVERSITY AT BUFFALO
Accounting Research Assistant STE212 DBA YUMI KIM - New York, NY
Bookkeeper (Full Charge)
Education:
UNIVERSITY AT BUFFALO, THE STATE UNIVERSITY OF NEW YORK - Buffalo, NY
Master of Science in Accounting UNIVERSITY AT BUFFALO, THE STATE UNIVERSITY OF NEW YORK - Buffalo, NY
Master of Art in Economics
Skills:
AUDIT, TAX, QUICKBOOKS, ADP, PAYCHEX, EXCEL
Chen Zhang Photo 56

Chen Zhang - Irvine, CA

Work:
Ogilvy & Mather - New York, NY 2011 to 2011
Interactive Designer Intern
Education:
Rochester Institute of Technology May 2010
Master of Fine Arts in December

Publications & IP owners

Us Patents

Hybrid Gate Stack Integration For Stacked Vertical Transport Field-Effect Transistors

US Patent:
2020036, Nov 19, 2020
Filed:
Aug 3, 2020
Appl. No.:
16/983587
Inventors:
- Armonk NY, US
Takashi Ando - Tuckahoe NY, US
Oleg Gluschenkov - Tannersville NY, US
Chen Zhang - Guilderland NY, US
Koji Watanabe - Rensselaer NY, US
International Classification:
H01L 21/8238
H01L 29/49
H01L 29/786
H01L 27/092
H01L 21/265
H01L 21/762
H01L 21/324
H01L 21/308
Abstract:
A method of forming a semiconductor structure includes forming one or more vertical fins each including a first semiconductor layer providing a vertical transport channel for a lower vertical transport field-effect transistor (VTFET) of a stacked VTFET structure, an isolation layer over the first semiconductor layer, and a second semiconductor layer over the isolation layer providing a vertical transport channel for an upper VTFET of the stacked VTFET structure. The method also includes forming a first gate stack including a first gate dielectric layer and a first gate conductor layer surrounding a portion of the first semiconductor layer of the vertical fins. The method further includes forming a second gate stack including a second gate dielectric layer and a second gate conductor layer surrounding a portion of the second semiconductor layer of the vertical fins. The first gate conductor layer and the second gate conductor layer are the same material.

Hybrid Gate Stack Integration For Stacked Vertical Transport Field-Effect Transistors

US Patent:
2020032, Oct 15, 2020
Filed:
Apr 15, 2019
Appl. No.:
16/384545
Inventors:
- Armonk NY, US
Takashi Ando - Tuckahoe NY, US
Oleg Gluschenkov - Tannersville NY, US
Chen Zhang - Guilderland NY, US
Koji Watanabe - Rensselaer NY, US
International Classification:
H01L 21/8238
H01L 21/324
H01L 21/308
H01L 21/762
H01L 21/265
H01L 27/092
H01L 29/786
H01L 29/49
Abstract:
A method of forming a semiconductor structure includes forming one or more vertical fins each including a first semiconductor layer providing a vertical transport channel for a lower vertical transport field-effect transistor (VTFET) of a stacked VTFET structure, an isolation layer over the first semiconductor layer, and a second semiconductor layer over the isolation layer providing a vertical transport channel for an upper VTFET of the stacked VTFET structure. The method also includes forming a first gate stack including a first gate dielectric layer and a first gate conductor layer surrounding a portion of the first semiconductor layer of the vertical fins. The method further includes forming a second gate stack including a second gate dielectric layer and a second gate conductor layer surrounding a portion of the second semiconductor layer of the vertical fins. The first gate conductor layer and the second gate conductor layer are the same material.

Possible Relatives

David Zhang  Dawei Zhang  Dazhi Zhang  De K Zhang  Da Q Zhang  Dachuan Zhang  Daijun Zhang  Chen Jun  Chen J Lee  Chen E Lim 

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