Chris V Vu, 542917 Rock River Ct, San Jose, CA 95111
Chris Vu Phones & Addresses
116 King Rd, San Jose, CA 95116 408-2547674
Livermore, CA
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Us Patents
Method And Test Apparatus For Testing Integrated Circuits Using Both Valid And Invalid Test Data
US Patent:
2006012, Jun 8, 2006
Filed:
Nov 17, 2004
Appl. No.:
10/992389
Inventors:
Chris Vu - Santa Clara CA, US
Assignee:
LSI Logic Corporation A Delaware Corporation - Milpitas CA
International Classification:
G01R 31/28
US Classification:
714726000
Abstract:
A simplified boundary scan test method capable of performing boundary test scanning of semiconductor chips. The test method comprises providing valid test data to a first terminal of the semiconductor device and purposely providing invalid test data to a second terminal of the semiconductor device in a predetermined pattern algorithm. Preload data is also preloaded onto the semiconductor device. The valid and invalid test data is then captured in the semiconductor device. If the captured data is as expected, it signifies that there is no problem with the boundary scan circuitry on the device. On the other hand if the captured data differs from what is expected, it signifies that there may be a problem with the boundary scan circuitry.
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