Christopher T Angell, 41Bellingham, WA

6323732, Nov 27, 2001

Jul 18, 2000

9/618736

Christopher W. Angell - Raleigh NC
Antonio Montalvo - Raleigh NC

Ericsson Inc. - Research Triangle Park NC

H03F 345

330261

Differential amplifiers include biasing circuits therein that can automatically account for process and/or temperature induced variations in. beta. and thereby more uniformly maintain the voltage gain of the differential amplifier at a desired level. A differential amplifier is provided that comprises first and second bipolar transistors electrically coupled together as an emitter-coupled pair (ECP) and a biasing circuit that is electrically connected to first and second emitters of the first and second bipolar transistors, respectively. This biasing circuit includes a current mirror that sets a magnitude of an emitter bias current in the first emitter at a value proportional to (. beta. +Z+1)/(. beta. +1), where. beta. is the gain of the first bipolar transistor and 1. ltoreq. Z. ltoreq. 2.

2018029, Oct 11, 2018

Apr 19, 2018

15/957766

- Norwood MA, US
David J. McLaurin - Raleigh NC, US
Christopher W. Angell - Cary NC, US
Sudhir Desai - Mansfield MA, US
Steven R. Bal - Cary NC, US

H03L 7/197
H03L 7/23
H03L 7/087
H04L 7/033
H03L 7/089
H03L 7/093
H03L 7/091
H04B 7/0413

Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.

2017032, Nov 9, 2017

May 5, 2016

15/147408

- Norwood MA, US
David J. McLaurin - Raleigh NC, US
Christopher W. Angell - Cary NC, US
Sudhir Desai - Mansfield MA, US
Steven R. Bal - Cary NC, US

H03L 7/197
H03L 7/093
H03L 7/089
H03L 7/091
H04L 7/033
H04B 7/0413

Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.

2015026, Sep 17, 2015

Jun 1, 2015

14/726913

- Hamilton, BM
Christopher W. Angell - Cary NC, US
Michael F. Keaveney - Lisnagry, IE

H03L 7/197
H03L 7/199

Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.

2015008, Mar 26, 2015

Sep 24, 2013

14/034917

- Hamilton, BM
Christopher W. Angell - Cary NC, US
Michael F. Keaveney - Lisnagry, IE

Analog Devices Technology - Hamilton

H03L 7/085
H03L 7/10

327142

Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.