Kin P Cheung, 73401 S Norfolk St APT 117, San Mateo, CA 94401

4509140, Apr 2, 1985

Jun 24, 1982

6/391778

Kin L. Cheung - Lowell MA

Wang Laboratories, Inc. - Lowell MA

G06F 304

364900

A communication network (10) has a memory unit (20) accessable to all ports (16-0, 16-1, 16-2, 16-3) of the link with a plurality of local sections (62) each associated with one of the ports. Interconnections include a dual memory bus (28) with a common bus subsystem (36) providing access to a common memory section and a local bus subsystem (30) providing access to the local memory sections, the subsystems constructed to permit concurrent independent use. Memory access priority circuitry (68) designates for each memory operating cycle a port for current service and makes memory access available to other elements when not required by the designated port.

4916603, Apr 10, 1990

Mar 18, 1985

7/170483

Robert P. Ryan - Marlborough MA
Kin L. Cheung - North Andover MA

Wang Labortatories, Inc. - Lowell MA

G06F 1208
G06F 1206

364200

A distributed reference and change table 36 for a virtual memory system 10 has a number of storage locations at least equal to the maximum number of data blocks of an associated read/write physical memory. A memory module 24 has a plurality of data words organized into n number of data blocks. The memory module includes an integral reference and change table having at least n storage locations each having at least two bits, one bit indicating the occurrence of an access (reference) to a corresponding data block and the other bit indicating if the access was a write (or change) type of access. A plurality of such memory modules are physically and electrically coupled to a common memory carrier module, each of the plurality of memory modules having an integral reference and change table.

5155834, Oct 13, 1992

Jan 11, 1990

7/463640

Robert P. Ryan - Marlborough MA
Kin L. Cheung - North Andover MA

Wang Laboratories, Inc. - Lowell MA

G06F 1300
G06F 936

395425

In a multi-processor virtual memory system 10 a Reference and Change Table (RCT) 36 is located upon a Memory Control Unit (MCU) 25. The RCT 36 is responsive to accesses to any of the Memory Modules (MMs) 24-26 and generates and maintains status bits indicative of the reference and change activity of all of page frames of the system memory that are accessible by any of the CPUs 12A-12n. In that each of the CPUs 12A-12n has access to the page frames of the system memory each of the CPUs 12A-12n is further enabled, via privileged instructions, to test (read) and reset (clear) over a system bus 16 the memory page frame status bits that are generated and stored by the RCT 36. As such, the RCT provides to multiple data processors a centralized and readily accessible store of status information relating to page frames of the system memory.

5062036, Oct 29, 1991

Apr 3, 1989

7/333818

Arthur Barrow - Acton MA
Kin L. Cheung - Andover MA
Jeffrey W. Einarson - Chelmsford MA
Shams A. Khan - Groton MA

Wang Laboratories, Inc. - Lowell MA

G06F 938
G06F 932
G06F 9355

364200

Instruction prefetching apparatus particularly adapted to executing an EXECUTE instruction specifiying a single subject instruction. The apparatus includes a first and second separately-controllable instruction syllable register and control apparatus. Under control of the control apparatus, the first instruction syllable register receives only the first syllable of the prefetched instruction; the second instruction syllable register receives all other syllables. The instruction syllable registers may be loaded either directly from memory or from a data register internal to the CPU. In the first case, the address of the instruction syllable to be prefetched is contained in a special instruction address register which is incremented each time an instruction syllable register is loaded. In the second case, the loading does not affect the value of the instruction address register. Also disclosed is a method of prefetching in which the first instruction syllable is prefetched into the first instruction syllable register and each of the other syllables is prefetched in turn to the second instruction syllable register and a method of executing the EXECUTE instruction in which the syllables of the EXECUTE instruction are prefetched directly from memory using the instruction address and the syllables of the subject instruction are fetched into the data register and from there into the instruction syllable registers.