Christopher Chun, 36Plano, TX

6753719, Jun 22, 2004

Aug 26, 2002

10/227893

Gayathri A. Bhagavatheeswaran - Austin TX
Hong Tian - Austin TX
Christopher Chun - Austin TX

Motorola, Inc. - Schaumburg IL

H03K 301

327534

A well bias controller receives input from a sensor. The sensor indicates when a desired threshold condition, such as a temperature or current limit has been exceeded. Threshold conditions are chosen so that when the threshold condition is exceeded, the amount of current drawn by the well bias circuit and through the transistor exceeds the amount of leakage current that would otherwise occur in the device if a well bias circuit were not used. Whenever it is determined, based on the threshold condition, that the well bias circuit is using more current than a device would otherwise leak, the controller turns the well bias circuit off.

6794949, Sep 21, 2004

Mar 28, 2003

10/402647

Gayathri Bhagavatheeswaran - Austin TX
Christopher Chun - Austin TX

Freescale Semiconductor, Inc. - Austin TX

H03F 100

331160, 331 1 A, 331177 R, 331 16

A system and method of varying frequency is disclosed. A first oscillator in a phase-locked loop (PLL) maintains a first frequency as part of the PLL lock. A second oscillator having a control coupled to the PLL can be modified to generate a frequency different than that of the PLL. This is accomplished while maintaining lock of the PLL.

6856173, Feb 15, 2005

Sep 5, 2003

10/656051

Christopher K. Chun - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H03K019/084

326108, 326105, 326 81, 326 68, 326113, 327333

An integrated circuit () includes a multiple voltage digital multiplexer circuit () for multiplexing digital signals provided at different supply voltage levels. In one form, the multiplexer () includes an analog multiplexer () for receiving the digital signals, a level shifter () coupled to the output of the analog multiplexer (), and a supply voltage multiplexer () for providing one of various supply voltages used on the IC corresponding to the signals being multiplexed. A control circuit () is used to control the input selection of the analog multiplexer () as well as the supply voltage multiplexer () for providing the correct supply voltage to the level shifter (). This provides the ability to multiplex digital signals of differing voltage levels onto a single pad on the IC ().

7181188, Feb 20, 2007

Mar 23, 2004

10/806498

Mieu Van Vu - Austin TX, US
Christopher K. Chun - Austin TX, US
Arthur M. Goldberg - Parkland FL, US
David J. Hayes - Lake Worth FL, US
Charbel Khawand - Miami FL, US
Jianping Tao - Cedar Park TX, US
John J. Vaglica - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H04B 1/16

4553432, 4553435, 455574, 713322

A method and apparatus for entering a low power mode is provided. In one embodiment, data processing system () has power control circuitry () which may be used to control power usage in data processing system (). Power mode select circuitry () may be used to select a power mode. Depending upon the power mode selected, power control circuitry () may use a cascaded approach to selecting which portions of data processing system () will be powered down, and thus how deeply data processing system () will be powered down.

7779284, Aug 17, 2010

Feb 23, 2007

11/678440

Bhoodev Kumar - Austin TX, US
Christopher K. Chun - Austin TX, US
Milind P. Padhye - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G06F 1/00
G06F 1/26
G06F 1/32
G06F 13/24

713324, 713300, 713320, 713323, 710262

A technique of operating a processor subsystem masks interrupts to the processor subsystem during a power-down sequence of a processor of the processor subsystem. A boot vector for the processor of the processor subsystem is set. The boot vector provides an address associated with a saved processor state. A current state of the processor is saved to provide the saved processor state. The technique determines whether one or more first masked interrupts occurred during the saving of the current state of the processor. The processor that is to be powered-down is stopped when the one or more first masked interrupts did not occur during the saving of the current state of the processor. The technique also determines whether one or more second masked interrupts occurred following the saving of the current state of the processor. The processor is powered-down when the one or more second masked interrupts did not occur following the saving of the current state of the processor.

2004015, Aug 19, 2004

Feb 14, 2003

10/366842

Christopher Chun - Austin TX, US
Der Sheu - Austin TX, US

H01L027/10

257/204000, 257/202000, 257/206000, 257/207000

Well bias circuitry for selectively biasing the voltages of the well areas of an integrated circuit. In one embodiment, the well bias circuitry includes a switching cell located in a row of cells of the integrated circuit for selectively coupling a voltage supply line to a well bias line. The switching cell may include two level shifters, each for providing a voltage to a gate of a coupling transistor to make the coupling transistor non conductive in response to an enable signal. The switching cells may be sequentially coupled such that the coupling transistors of each of the switching cells are not made conductive at the same time so as to reduce inrush current due to changing the well bias from a well bias voltage to a supply voltage. In one example, the switching cells may include delay circuitry for delaying the change in state of the enable signal before being provided to the next switching cell.

2005005, Mar 17, 2005

Sep 12, 2003

10/660847

Shivraj Dharne - Noida, IN
Shahid Ali - New Delhi, IN
Christopher Chun - Austin TX, US
Claude Moughanni - Austin TX, US

H03L005/00

327333000

A level shifter for an integrated circuit. In one embodiment, the level shifter is a bi-directional level shifter with a signal terminal located in each voltage domain that can be utilized as input or output terminal. In some embodiments, the level shifter includes transistors for cutting off the flow of current between domain power supplies when the input terminals are at a particular state. In one embodiment, only one signal line of the level shifter crosses a domain boundary.

2005006, Mar 31, 2005

Sep 30, 2003

10/675005

Ryan Bedwell - Kyle TX, US
Christopher Chun - Austin TX, US
Qadeer Qureshi - Dripping Springs TX, US
John Vaglica - Austin TX, US

G11C007/00
G11C005/06

365063000, 365226000, 365189120

Leakage current is eliminated in a memory array during a low power mode of a processing system having a processor that interfaces with the memory array. Because two power planes are created, the processor may continue executing instructions using a system memory while bypassing the memory array when the array is powered down. A switch selectively removes electrical connectivity to a supply voltage terminal in response to either processor-initiated control resulting from execution of an instruction or from a source originating in the system somewhere else than the processor. Upon restoration of power to the memory array, data may or may not need to be marked as unusable depending upon which of the two power planes supporting arrays to the memory array are located. Predetermined criteria may be used to control the timing of the restoration of power. Multiple arrays may be implemented to independently reduce leakage current.