Chun W Chan, 5210201 S Foothill Blvd, Cupertino, CA 95014

6425114, Jul 23, 2002

Jan 31, 2000

09/494605

Chun Chan - Sunnyvale CA
Bing Yi - Sunnyvale CA

LSI Logic Corporation - Milpitas CA

G06F 1750

716 6, 716 5

Skew is reduced in a tree-shaped distribution network having plural levels and plural nodes at each level, where a node at one level connects to plural nodes at the next lower level. Initially, the current level is set to the bottom level of the network. Delay ranges are then obtained corresponding to nodes at the current level and the delay ranges are shifted in an attempt to align delay ranges corresponding to nodes at the current level that connect to the same node at the next higher level. These steps are then repeated for all levels in order from the bottom level to the top level.

6480989, Nov 12, 2002

Jun 29, 1998

09/106890

Chun Chan - San Jose CA
Tammy Huang - Fremont CA
Mike Liang - Milpitas CA

LSI Logic Corporation - Milpitas CA

G06F 1750

716 8, 257211, 716 11, 716 14

Provided is a technique for designing an integrated circuit die which includes a semiconductor layer, a primary metal layer, a horizontal metal layer and a vertical metal layer. Electronic components are laid out on the semiconductor layer, and a primary power distribution network for distributing power to the electronic components is laid out on the primary metal layer. Then, a uniform trunk width is calculated for all trunks in a power mesh based on a desired maximum voltage drop for the generated electronic component layout. Finally, horizontal power trunks are laid out on the horizontal metal layer and vertical power trunks are laid out on the vertical metal layer using the calculated uniform trunk width, so as to form the power mesh, and an electrical connection is specified between the power mesh and the primary power distribution network.

6492736, Dec 10, 2002

Mar 14, 2001

09/808441

Chun Chan - Sunnyvale CA
Bo Shen - Fremont CA

LSI Logic Corporation - Milpitas CA

H01L 2348

257773, 257750, 257758, 257920

A multiple layer mesh design that provides that a bridge associated with a second layer connects a rail on a first layer to a trunk on a fourth layer. If the trunk on the third layer shadows a plurality of rails on the first layer, preferably the bridge is at least as wide as a sum of the widths of the rails on the first layer which are shadowed by the trunk on the third layer. If the trunk on the third layer shadows a single rail on the first layer, preferably the bridge is at least as wide as twice the width of the rail on the first layer.

7207021, Apr 17, 2007

Jan 14, 2005

11/036822

Qian Cui - San Jose CA, US
Chun Chan - Sunnyvale CA, US

LSI Logic Corporation - Milpitas CA

G06F 17/50

716 6, 703 14, 716 1

A method is provided for selecting a frequency-based ramptime limit for a technology. The method includes creating a logic chain with cells from the technology and applying a sequence of signals to the logic chain. Each signal has a different ramptime relative to a clock period. At least one signal quality characteristic is measured along the logic chain for each of the signals. The frequency-based ramptime limit is selected based on a comparison of the measured signal quality characteristics measured to at least one predefined signal quality value.

6323559, Nov 27, 2001

Jun 23, 1998

9/103654

Chun Chan - San Jose CA
Mike Liang - Milpitas CA

LSI Logic Corporation - Milpitas CA

H01L 2348

257778

A flip-chip integrated circuit die includes a semiconductor substrate, electronic components implemented on the semiconductor substrate, several plural metal layers, wires routed between the electronic components on the metal layers, a top layer, and bump pads arranged in a hexagonal array on the top layer. According to another aspect, the invention is directed to flip-chip integrated circuit design, in which a circuit description is input and standardized cells which correspond to electronic components in the circuit description are obtained. The standardized cells are laid out on the surface of the die using a rectangular-based layout technique, and bump pads are laid out in a hexagonal array.

2017008, Mar 23, 2017

Sep 16, 2016

15/268475

- Mountain View CA, US
Chun Chan - Cupertino CA, US
Che-Hua Shih - Zhubei City, TW
Chia-Chih Yen - Taipei City, TW

G06F 17/50

Techniques for equivalence checking of analog models are disclosed. The models include transistor level representations. The representations are used for simulation and verification of the circuit and are required to give similar output results in response to a given input stimulus. A common input stimulus is created for a first representation and a second representation of a semiconductor circuit. Output waveforms are generated for the first representation and the second representation using the common input stimulus. The first output waveforms and the second output waveforms are checked for equivalence. Signals from the first output waveforms are mapped to the second output waveforms.