Chung Desmond Lam, 53Ames, IA

6391703, May 21, 2002

Jun 28, 2001

09/894336

Nivo Rovedo - LaGrangeville NY
Chung H. Lam - Williston VT
Rebecca D. Mih - Wappingers Falls NY

International Business Machines Corporation - Armonk NY

H01L 218242

438241, 438244

A logic circuit including an embedded DRAM achieves process integration by simultaneously forming the strap connecting the memory cell capacitor with the pass transistor and a buried dielectric layer isolating the logic transistor sources and drains from the substrate.

6403482, Jun 11, 2002

Jun 28, 2000

09/605726

Nivo Rovedo - LaGrangeville NY
Chung Hon Lam - Williston VT

International Business Machines Corporation - Armonk NY

H01L 21302

438689, 438692, 438719, 438723

Transistors having self-aligned dielectric layers under the source/drain contacts are formed by constructing transistors up to the LDD implant; etching STI oxide selective to Si and nitride to form a self-aligned contact recess; depositing an insulating layer in the bottom of the contact recess; recessing the insulating layer to leave room for a conductive contact layer; depositing the contact layer to make contact on a vertical surface to the Si underneath the gate sidewalls; recessing the contact layer; forming interlayer dielectric and interconnect to complete the circuit.

6534807, Mar 18, 2003

Aug 13, 2001

09/928738

Jack A. Mandelman - Stormville NY
Dong Gan - Beacon NY
Chung H. Lam - Williston VT

International Business Machines Corporation - Armonk NY

H01L 2980

257272

A JOI structure and cell layout including at least one patterned gate stack region present atop a semiconductor substrate, said semiconductor substrate having source/drain diffusion regions of opposite dopant polarity abutting each other present therein, said source/drain diffusion regions are present atop an insulating layer, said insulating layer not being present beneath said at least one patterned gate stack region. An alternative JOI structure and cell layout of the present invention includes at least one patterned gate stack region present atop a semiconductor substrate, said semiconductor substrate containing at least a conductive region other than source/drain diffusion regions present atop an insulating layer embedded therein, said insulating layer not being present beneath said at least one patterned gate stack region, wherein said conductive region is in contact with vertical sidewalls of source/drain extension regions present in said semiconductor substrate, beneath said at least one patterned gate stack region.

6541815, Apr 1, 2003

Oct 11, 2001

09/974968

Jack A. Mandelman - Stormville NY
Louis L. Hsu - Fishkill NY
Chung H. Lam - Williston VT
Carl J. Radens - LaGrangeville NY

International Business Machines Corporation - Armonk NY

H01L 29788

257315, 257330

A 2F flash memory cell structure and a method of fabricating the same are provided. The 2F flash memory cell structure includes a Si-containing substrate having a plurality of trenches formed therein. Each trench has sidewalls that extend to a bottom wall, a length and individual segments that include two memory cell elements per segment. Each memory cell element comprises (i) a floating gate region having L-shaped gates formed on a portion of each trench sidewall; (ii) a program line overlapping one side of the L-shaped gates present at the bottom wall of each trench and extending along the entire length of the plurality of trenches; and (iii) a control gate region overlying the floating gate region. The control gate region includes gates formed on portions of the sidewalls of the trenches that are coupled to the floating gate regions. The memory cell structure further includes bitline diffusion regions formed in the Si-containing semiconductor substrate abutting each trench segment; and wordlines that lay orthogonal to the trenches.

6544874, Apr 8, 2003

Aug 13, 2001

09/928759

Jack A. Mandelman - Stormville NY
Kevin K. Chan - Staten Island NY
Bomy A. Chen - Ridgefield CT
Oleg Gluschenkov - Wappingers Falls NY
Rajarao Jammy - Wappingers Falls NY
Victor Ku - Tarrytown NY
Chung H. Lam - Williston VT
Nivo Rovedo - LaGrangeville NY

International Business Machines Corporation - Armonk NY

H01L 213205

438589

A method for forming a JOI structure which allows for reduction in both source/drain junction leakage and capacitance is provided. In the inventive method, an insulator layer is formed under the source/drain regions, but not under the channel region. The insulator layer is formed in the present invention after forming the gate stack region and recessing the semiconductor surface surrounding the gate stack region, followed by deposition of a conductive material such as polysilicon and, optionally, heavy source/drain diffusion formation.

6724029, Apr 20, 2004

Feb 21, 2002

09/683831

Louis L. Hsu - Fishkill NY
Chung H. Lam - Williston VT
Jack A. Mandelman - Stormville NY
Carl J. Radens - LaGrangeville NY
William R. Tonti - Essex Junction VT

International Business Machines Corporation - Armonk NY

H01L 27108

257296, 257239, 257301, 257302, 257306, 257316

A programmable memory cell structure that includes a pair of memory cells is provided. Each pair of memory cells includes a shared control gate and first and second floating gates present about the shared control gate. The first and second floating gates have respective gate regions disposed on respective sides of the control gate. Dielectric structures are present between the control gate and respective ones of the gate regions of the floating gates. The control gate and gates of the first and second floating gates are formed within a single lithographic square.

7233177, Jun 19, 2007

Apr 4, 2005

11/098078

Louis C. Hsu - Fishkill NY, US
Brian L. Ji - Fishkill NY, US
Chung Hon Lam - Peekskill NY, US

International Business Machines Corporation - Armonk NY

H03K 5/22
G06G 7/28

327 78, 327334

The present invention comprises a method and structure for programming an on-chip phase-change resistor to a target resistance. Using an off-chip precision resistor as a reference, a state-machine determines a difference between the resistance of an on-chip resistor and the target resistance. Based upon this difference, the state machine directs a pulse generator to apply set or reset pulses to the on-chip resistor in order to decrease or increase, respectively, the resistance of the resistor, as necessary. In order to program the resistance of the phase-change resistor to a tight tolerance, it is successively reset and set by applying progressively decreasing numbers of reset pulses and set pulses, respectively, until the number of set pulses is equal to one and the target resistance of the on-chip resistor is reached.

7319608, Jan 15, 2008

Jun 30, 2005

11/172473

Louis L. C. Hsu - Fishkill NY, US
Brian L. Ji - Fishkill NY, US
Chung Hon Lam - Peekskill NY, US

International Business Machines Corporation - Armonk NY

G11C 11/00

365163, 365104, 365149

A non-volatile content addressable memory cell comprises: a first phase change material element, the first phase change material element having one end connected to a match-line; a first transistor, the first transistor having a gate connected to a word-line, a source connected to a true bit-read-write-search-line, and a drain connected to another end of the first phase change material element; a second phase change material element, the second phase change material element having one end connected to the match-line; and a second transistor, the second transistor having a gate connected to the word-line, a source connected to a complementary bit-read-write-search-line, and a drain connected to another end of the second phase change material element.