Clarence W Teng, 725412 Glenshire Dr, Plano, TX 75093

5595925, Jan 21, 1997

Apr 29, 1994

8/236745

Ih-Chin Chen - Richardson TX
Hisashi Shichijo - Plano TX
Clarence W. Teng - Plano TX

Texas Instruments Incorporated - Dallas TX

H01L 2170
H01L 2700

437 52

A dynamic random access memory device (10) includes three separate sections--an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n-type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).

5894145, Apr 13, 1999

Aug 12, 1997

8/909904

Ih-Chin Chen - Richardson TX
Hisashi Shichijo - Plano TX
Clarence W. Teng - Plano TX

Texas Instruments Incorporated - Dallas TX

H01L 27108

257296

A dynamic random access memory device (10) includes three separate sections--an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n- type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).

4538343, Sep 3, 1985

Jun 15, 1984

6/620995

Gordon P. Pollack - Richardson TX
Clarence Teng - Plano TX
William R. Hunter - Garland TX

Texas Instruments Incorporated - Dallas TX

H01L 2131
H01L 2176

29576W

A sidewall-nitride isolation technology avoids stress-induced defects, while permitting a heavy channel stop implant to avoid turn-on of the field oxide transistor, by performing a two-step silicon etch. The first channel stop implant is performed after the first silicon etch, before the sidewall nitride is deposited. A further silicon etch is performed after the sidewall nitride is in place, and a second channel stop implant follows. The first implant can be a light dose, to avoid excess subthreshold leakage in the active devices due to field-assisted turn on at the corners of the moat regions, and the second implant can be a very heavy dose to provide complete isolation without any danger of the channel stop species encroaching on the active device regions.

4916524, Apr 10, 1990

Jan 23, 1989

7/300467

Clarence W. Teng - Plano TX
Robert R. Doering - Plano TX
Ashwin H. Shah - Dallas TX

Texas Instruments Incorporated - Dallas TX

H01L 2978
H01L 2906
H01L 2702

357 236

The described embodiments of the present invention provide structures, and a method for fabricating those structures, which include a memory cell formed within a single trench. A trench is formed in the surface of a semiconductor substrate. The bottom portion of the trench is filled with polycrystalline silicon to form one plate of a storage capacitor. The substrate serves as the other plate of the capacitor. The remaining portion of the trench is then filled with an insulating material such as silicon dioxide. A pattern is then etched into the silicon dioxide when opens a portion of the sidewall and the top portion of the trench down to the polycrystalline capacitor plate. A contact is then formed between the polycrystalline capacitor plate and the substrate. Dopant atoms diffuse through the contact to form a source region on a sidewall of the trench. A gate insulator is formed by oxidation and a drain is formed at the surface of the trench adjacent to the mouth of the trench.

4987093, Jan 22, 1991

Oct 24, 1989

7/426824

Clarence W. Teng - Plano TX
Roger A. Haken - Dallas TX

Texas Instruments Incorporated - Dallas TX

H01L 21265
H01L 2176

437 69

Preferred embodiments include channel stop implants for CMOS devices by through field boron implants (152) after the field oxide (144, 145) has been grown and with the implant depth determined by the thin portions of the field oxide (145). Junction (154) breakdown is preserved by channeling the implant (152) to penetrate far below the junctions (154).

5043778, Aug 27, 1991

Aug 25, 1988

7/238978

Clarence W. Teng - Dallas TX
Thomas E. Tang - Plano TX
Che-Chia Wei - Plano TX

Texas Instruments Incorporated - Dallas TX

H01L 2978
H01L 2702
H01L 2904
H01L 2712

357 233

A MOS bulk device having source/drain-contact regions 36 which are almost completely isolated by a dielectric 35. These "source/drain" regions 36 formed by using a silicon etch to form a recess, limiting the etched recess with oxide, and backfilling with polysilicon. A short isotropic oxide etch, followed by a polysilicon filament deposition, then makes contact between the oxide-isolated source/drain-contact regions 36 and the channel region 33 of the active device. Outdiffusion through the small area of this contact will form small diffusioins 44 in silicon, which act as the electrically effective source/drain regions. Use of sidewall nitride filaments 30 on the gate permits the silicon etch step to be self-aligned.

5061653, Oct 29, 1991

Oct 30, 1990

7/605818

Clarence W. Teng - Plano TX

Texas Instruments Incorporated - Dallas TX

H01L 2176

437 67

The disclosure relates to the article and a method of forming a field oxide which extends over an isolation trench and the adjacent substrate wherein a portion of the trench insulating sidewall at the top region thereof is removed and replaced by polysilicon. The exposed silicon on the substrate and adjacent polysilicon are than oxidized to form the field oxide which is continuous, disposed above and contacts the remaining sidewall insulator in the trench.

4890147, Dec 26, 1989

Apr 15, 1987

7/038388

Clarence W. Teng - Plano TX
Roger A. Haken - Dallas TX

Texas Instruments Incorporated - Dallas TX

H01C 2977

357 2311

Preferred embodiments include channel stop implants for CMOS devices by through field boron implants (152) after the field oxide (144, 145) has been grown and with the implant depth determined by the thin portions of the field oxide (145). Junction (154) breakdown is preserved by channeling the implant (152) to penetrate far below the junctions (154).