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Clarence W Teng, 664301 Denver Dr, Plano, TX 75093

Clarence Teng Phones & Addresses

4301 Denver Dr, Plano, TX 75093    972-8672725    972-9851199   

1789 Linnet Ln, Sunnyvale, CA 94087    408-2557386   

Carrollton, TX   

Dallas, TX   

Santa Clara, CA   

Mabank, TX   

Grand Prairie, TX   

5412 Glenshire Dr, Plano, TX 75093    214-4505394   

Work

Position: Healthcare Support Occupations

Education

Degree: Bachelor's degree or higher

Mentions for Clarence W Teng

Public records

Vehicle Records

Clarence Teng

Address:
5412 Glenshire Dr, Plano, TX 75093
VIN:
5NMSH73E17H040454
Make:
HYUN
Model:
SANT
Year:
2007

Business Records

Name / TitleCompany / ClassificationPhones & Addresses
Clarence W. Teng
Chief Executive Offi, Director
Being Advanced Memory Corporation 12200 Frd Rd, Dallas, TX 75234
1115 4 Ave, Carrollton, TX 75006

Publications

Us Patents

Method For Fabricating A Multiple Well Structure For Providing Multiple Substrate Bias For Dram Device Formed Therein

US Patent:
5595925, Jan 21, 1997
Filed:
Apr 29, 1994
Appl. No.:
8/236745
Inventors:
Ih-Chin Chen - Richardson TX
Hisashi Shichijo - Plano TX
Clarence W. Teng - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2170
H01L 2700
US Classification:
437 52
Abstract:
A dynamic random access memory device (10) includes three separate sections--an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n-type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).

Process Of Making Ic Isolation Structure

US Patent:
4660278, Apr 28, 1987
Filed:
Jun 26, 1985
Appl. No.:
6/749952
Inventors:
Clarence W. Teng - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2120
H01L 21302
US Classification:
29576W
Abstract:
Using a structure according to one embodiment of the present invention, active elements in integrated circuitry may be completely isolated from other elements in the integrated circuitry by silicon dioxide regions surrounding the sides of the region containing the active element and a buried diffusion beneath the active element extending to all sides of the isolating silicon dioxide regions. In one embodiment of the present invention, an isolation structure is fabricated by etching a silicon substrate to remove the silicon from the entire region occupied by the isolated active area and the isolation structure of this embodiment of the invention. A conformal layer of silicon dioxide, or other dielectric material, is then deposited on the surface of the silicon substrate. The conformal silicon dioxide layer is then anisotropically etched to remove the silicon dioxide on the bottom of the isolation region but still provide a sidewall region of silicon dioxide on the sides of the isolation region. The bottom of the isolation region is then implanted with dopant ions to provide a depletion region in the bottom of the isolation region.

Dram Cell And Method

US Patent:
4864375, Sep 5, 1989
Filed:
Apr 29, 1988
Appl. No.:
7/188729
Inventors:
Clarence W. Teng - Plano TX
Cheng-Eng D. Chen - Richardson TX
Bor-Yen Mao - Richardson TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2978
H01L 2702
H01L 2906
H01L 2712
US Classification:
357 236
Abstract:
The following detailed description describes a dynamic random access memory (dRAM) cell. The described cell provides a one-transistor/one-capacitor dRAM cell structure and array in which the cell pass transistor is formed on the sidewalls of a trench containing the cell capacitor; the word and bit lines cross over this trench. The trench extends through an epitaxial layer into a substrate. The epitaxial layer and substrate are separated by a layer which serves as a diffusion barrier. This stacking of the transistor on top of the capcitor yields a cell with minimal area on the substrate and solves a problem of dense packing of cells. The diffusion barrier allows for the optimal doping of the epitaxial for operation of the transistor and optimal doping of the substrate for operation of the capacitor. One capacitor plate and the transistor channel and source region are formed in the bulk sidewall of the trench, and the transistor gate and the other plate of the capacitor are both formed in polysilicon in the trench but separated from each other by an oxide layer inside the trench. The signal charge is transferred to the polysilicon capacitor plate transistor with the polysilicon capacitor plate.

Trench Capacitor Memory Cell With Curved Capacitors

US Patent:
5111259, May 5, 1992
Filed:
Jul 25, 1989
Appl. No.:
7/385340
Inventors:
Clarence Teng - Plano TX
Peter Ying - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2968
H01L 2144
US Classification:
357 236
Abstract:
The described embodiments of the present invention provide DRAM cells, structures and manufacturing methods. In a first embodiment, a DRAM cell with a trench capacitor having a first plate formed as a diffusion on the outside surface of a trench formed in the substrate and a second plate having a conductive region formed inside the trench is fabricated. In another embodiment of the present invention, a planar capacitor is used with a field plate isolation scheme including a transfer transistor moat region self-aligned to the field plate. This structure allows the elimination of alignment tolerances between the capacitor and the transistor thus reducing the space necessary between the transistor and the capacitor. In another embodiment of the present invention, a memory cell using two conductive plates formed inside a trench as the storage capacitor is fabricated. A field plate isolation scheme which allows for self-alignment of the moat containing the transfer transistor is used thus allowing for self-alignment of the moat and elimination of alignment tolerances between the moat region and the source drain diffusions.

Defect Free Trench Isolation Devices And Method Of Fabrication

US Patent:
4983226, Jan 8, 1991
Filed:
Mar 15, 1990
Appl. No.:
7/494811
Inventors:
William R. Hunter - Garland TX
Christopher Slawinski - Austin TX
Clarence W. Teng - Plano TX
Assignee:
Texas Instruments, Incorporated - Dallas TX
International Classification:
H01L 2930
H01L 2702
US Classification:
148 332
Abstract:
The specification discloses an isolation trench (36) formed in a semiconductor body. A stress relief layer (38) of oxide is formed on the interior walls of the trench (36), the layer (38) being sufficiently thin to prevent stressing of the lower corners of the trench (36). A masking layer (40) of nitride is formed over the layer (38). An isolation body (42) of oxide or polysilicon then refills the remainder of the trench and a cap oxide (43) and layer (44) of field oxide is formed over the semiconductor body and the filled trench.

High Density Dynamic Ram Cell

US Patent:
5057887, Oct 15, 1991
Filed:
Jun 14, 1989
Appl. No.:
7/366801
Inventors:
Masaaki Yashiro - Plano TX
Shigeki Morinaga - Tsuchiura,
Clarence W. Teng - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2968
H01L 2906
H01L 2940
US Classification:
357 236
Abstract:
The described embodiments of the present invention provide a memory cell and method for fabricating that memory cell and memory array including the cell. The memory cell is a trench capacitor type having a transistor (1-1-2) formed on the surface of a major face of a substrate (16) and having a capacitor (2-1-2) formed in the substrate around the periphery of a trench. The capacitor and transistor are connected by a buried, heavily doped region (26) having the opposite conductivity type from the substrate. A doped storage area (24) having the same doping type as the buried doped region surrounds the trench. A field plate (30) is formed in the trench separated from the storage region by a dielectric layer (32). The field plate extends onto the isolation areas between memory cells thus providing isolation between cells using a minimum of surface area. A self-aligned process is used to form the source (14) and drain (12) for the pass gate transistor and automatic connection between the source of the transistor and the buried doping layer is made by the buried N+ layer.

Integrated Circuit Fabrication Method Utilizing Selective Etching And Oxidation To Form Isolation Regions

US Patent:
4561172, Dec 31, 1985
Filed:
Jun 15, 1984
Appl. No.:
6/621023
Inventors:
Christopher Slawinski - Dallas TX
Robert R. Doering - Plano TX
Clarence W. Teng - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21302
H01L 2176
US Classification:
29576W
Abstract:
A sidewall-nitride isolation technology refines process control over lateral oxide encroachment by preventing any thinning of the nitride moat-masking layer during the nitride etch step which clears the sidewall nitride layer from the bottom of the etched recesses in silicon. This is done by initially patterning the moat regions in an oxide/nitride/oxide stack, rather than the nitride/oxide stack of the prior art.

Contact Etch Process

US Patent:
5087591, Feb 11, 1992
Filed:
Mar 16, 1988
Appl. No.:
7/169078
Inventors:
Clarence W. Teng - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21302
US Classification:
437225
Abstract:
Contact etching is simplified by including a conformal etch stop layer underneath the interlevel or multilevel oxide (MLO). Etching through the unequal thickness of the MLO with sufficient overetching to reliably clear the thickest parts of the MLO layer will therefore not damage the silicon contact areas underneath the thinner parts of the MLO. Process control is also improved. Preferably this conformal etch stop layer is a conductor, and is grounded to configure a field plate over the entire surface of the chip.

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