Robert M Bertin, 82290 Teton Dr, Saulsbury, TN 38067

6034399, Mar 7, 2000

Mar 6, 1997

8/812183

Frederick T. Brady - Chantilly VA
Robert C. Bertin - Fairfax VA

Lockheed Martin Corporation - Bethesda MD

H01L 2362
H01L 2701
H01L 2712
H01L 2900

257355

An ESD protection arrangement for a silicon-on-insulator device has an N-well type implant in the silicon substrate of the device, a p. sup. + implant forming a juncture with the N-well type implant, and an n. sup. + implant defining a juncture with the N-well type implant, in order to protect against negative transients and positive transients. At the p-channel threshold adjust, both the p-channel of the device and the N-well are implanted. Implanting the N-well to a depth of about 0. 15 to about 0. 30. mu. m provides suitable characteristics for both the N-well and the p-channel.

6111780, Aug 29, 2000

Jun 4, 1999

9/325645

Robert Christian Bertin - Fairfax VA

Lockheed Martin Corporation - Bethesda MD

G11C 1100

365154

A memory device can include a radiation hardened, static random access memory (SRAM) cell having a first inverter pair including a first PFET and a first NFET coupled in series drain to drain by a resistor whose resistance can be an order of magnitude (i. e. , ten times) larger than the source to drain resistance of the first PFET, a second inverter pair including a second PFET and a second NFET coupled in series drain to drain by a resistor whose resistance can be an order of magnitude larger than the source to drain resistance of the second PFET, the first or second PFET can include a P+ drain difflusion in an NWELL where a portion of the gate can overlie the P+ drain diffusion, a first pass gate PFET coupled to the gate of the first PFET, the gate of the first NFET, and the P+ drain diffusion of the second PFET, and a second pass gate PFET coupled to the gate of the second PFET, the gate of the second NFET, and the P+ drain diffusion of the first PFET.