Craig D Keefer, 705 Rodman St, Nashua, NH 03064

6353877, Mar 5, 2002

Apr 18, 2000

09/551633

Samuel Hammond Duncan - Arlington MA
Glenn Arthur Herdeg - Leominster MA
Ricky Charles Hetherington - Westboro MA
Craig Durand Keefer - Nashua NH
Maurice Bennet Steinman - Marlboro MA
Paul Michael Guglielmi - Westboro MA

Compaq Computer Corporation - Houston TX

G06F 1212

711155, 711144, 711145, 711133, 710129, 710126

A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units incorporates cache coherency protocol and an enhanced invalidation scheme to ensure atomicity, which minimizes the bus utilization. In addition, a method for allowing peer-to-peer communication between I/O devices coupled to the system bus via different I/O bridges includes a command and address space configuration that allows for communication without the involvement of any central processing device. Interrupt performance is improved through the storage of an interrupt data structure in main memory. The I/O bridges maintain the data structure, and when the CPU is available the interrupts can be accessed by a fast memory read; thereby reducing the requirement of I/O reads for interrupt handling.

6128711, Oct 3, 2000

Nov 12, 1996

8/745553

Samuel Hammond Duncan - Arlington MA
Glenn Arthur Herdeg - Leominster MA
Ricky Charles Hetherington - Westboro MA
Craig Durand Keefer - Nashua NH
Maurice Bennet Steinman - Marlboro MA
Paul Michael Guglielmi - Westboro MA

Compaq Computer Corporation - Houston TX

G06F 1212

711155

A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units incorporates cache coherency protocol and an enhanced invalidation scheme to ensure atomicity which minimizing the bus utilization. In addition, a method for allowing peer-to-peer communication between I/O devices coupled to the system bus via different I/O bridges includes a command and address space configuration that allows for communication without the involvement of any central processing device. Interrupt performance is improved through the storage of an interrupt data structure in main memory. The I/O bridges maintain the data structure, and when the CPU is available the interrupts can be accessed by a fast memory read; thereby reducing the requirement of I/O reads for interrupt handling.

6249520, Jun 19, 2001

Oct 24, 1997

8/957664

Simon C. Steely - Hudson NH
Stephen R. VanDoren - Northborough MA
Craig D. Keefer - Nashua NH
David W. Davis - Lexington MA

Compaq Computer Corporation - Houston TX

H04L 1250

370368

An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP.

5953538, Sep 14, 1999

Nov 12, 1996

8/748145

Samuel Hammond Duncan - Arlington MA
Craig Durand Keefer - Nashua NH
Thomas Adam McLaughlin - Worcester MA
Paul Michael Guglielmi - Westboro MA

Digital Equipment Corporation - Houston TX

G06F 1200
G06F 1300

395842

A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units incorporates cache coherency protocol and an enhanced invalidation scheme to ensure atomicity which minimizing the bus utilization. In addition, a method for allowing peer-to-peer communication between I/O devices coupled to the system bus via different I/O bridges includes a command and address space configuration that allows for communication without the involvement of any central processing device. Interrupt performance is improved through the storage of an interrupt data structure in main memory. The I/O bridges maintain the data structure, and when the CPU is available the interrupts can be accessed by a fast memory read; thereby reducing the requirement of I/O reads for interrupt handling.

6012120, Jan 4, 2000

Mar 18, 1999

9/271558

Samuel Hammond Duncan - Arlington MA
Craig Durand Keefer - Nashua NH
Thomas Adam McLaughlin - Worcester MA
Paul Michael Guglielmi - Westboro MA

Digital Equipment Corporation - Houston TX

G06F 1300

710129

A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units incorporates cache coherency protocol and an enhanced invalidation scheme to ensure atomicity which minimizing the bus utilization. In addition, a method for allowing peer-to-peer communication between I/O devices coupled to the system bus via different I/O bridges includes a command and address space configuration that allows for communication without the involvement of any central processing device. Interrupt performance is improved through the storage of an interrupt data structure in main memory. The I/O bridges maintain the data structure, and when the CPU is available the interrupts can be accessed by a fast memory read; thereby reducing the requirement of I/O reads for interrupt handling.

2020005, Feb 13, 2020

Aug 9, 2019

16/536745

- Hamilton, BM
John M. Chaves - Hudson MA, US
Andrew Alden - Leominster MA, US
Craig D. Keefer - Nashua NH, US
Christopher D. Cotton - Nashua NH, US
Michael Egan - Groton MA, US

STRATUS TECHNOLOGIES BERMUDA, LTD. - Hamilton

G06F 11/20
G06F 13/28
G06F 13/40
G06F 13/42

A fault tolerant computer system and method are disclosed. The system may include a plurality of CPU nodes, each including: a processor and a memory; at least two IO domains, wherein at least one of the IO domains is designated an active IO domain performing communication functions for the active CPU nodes; and a switching fabric connecting each CPU node to each IO domain. One CPU node is designated a standby CPU node and the remainder are designated as active CPU nodes. If a failure, a beginning of a failure, or a predicted failure occurs in an active node, the state and memory of the active CPU node are transferred to the standby CPU node which becomes the new active CPU node. If a failure occurs in an active IO domain, the communication functions performed by the failing active IO domain are transferred to the other IO domain.