Cung D Tran, 5733 Gala Pl, Niskayuna, NY 12309

8236637, Aug 7, 2012

Sep 29, 2010

12/893245

Henry K. Utomo - Hopewell Junction NY, US
Sameer Hemchand Jain - Hopewell Junction NY, US
Ravikumar Ramachandran - Hopewell Junction NY, US
Cung D. Tran - Hopewell Junction NY, US

International Business Machines Corporation - Armonk NY

H01L 21/8238

438199, 438229, 438300, 257E21634

A planar silicide structure and method of fabrication is disclosed. A FET having a silicided raised source-drain structure is formed where the height of the source-drain structures are the same as the height of the gates, simplifying the process of forming contacts on the FET. One embodiment utilizes a replacement metal gate FET and another embodiment utilizes a gate-first FET.

8298934, Oct 30, 2012

Jun 7, 2011

13/155056

Jeffery B. Maxson - New Windsor NY, US
Cung Do Tran - Newburgh NY, US
Huilong Zhu - Poughkeepsie NY, US

International Business Machines Corporation - Armonk NY

H01L 21/4763

438627, 438630, 257377, 257382, 257384, 257388, 257413, 257E21584

The semiconductor structure is provided that has entirely self-aligned metallic contacts. The semiconductor structure includes at least one field effect transistor located on a surface of a semiconductor substrate. The at least one field effect transistor includes a gate conductor stack comprising a lower layer of polysilicon and an upper layer of a first metal semiconductor alloy, the gate conductor stack having sidewalls that include at least one spacer. The structure further includes a second metal semiconductor alloy layer located within the semiconductor substrate at a footprint of the at least one spacer. The structure also includes a first metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the first metal semiconductor alloy layer and a second metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the second metal semiconductor alloy layer.

8415250, Apr 9, 2013

Apr 29, 2011

13/097459

Emre Alptekin - Wappingers Falls NY, US
Viraj Yashawant Sardesai - Poughkeepsie NY, US
Cung Do Tran - Newburgh NY, US
Jian Yu - Danbury CT, US
Reinaldo Ariel Vega - Wappingers Falls NY, US
Rajasekhar Venigalla - Hopewell Junction NY, US

International Business Machines Corporation - Armonk NY

H01L 29/417

438666, 257E29116, 257410, 257773, 438300

A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.

8492275, Jul 23, 2013

Jul 20, 2011

13/186519

Emre Alptekin - Wappingers Falls NY, US
Viraj Y. Sardesai - Poughkeepsie NY, US
Cung D. Tran - Newburgh NY, US
Bin Yang - Yorktown Heights NY, US

International Business Machines Corporation - Armonk NY
GlobalFoundries, Inc. - Grand Cayman

H01L 21/44

438682, 438630, 257E21438, 257E21439

Methods form an integrated circuit structure by forming at least a portion of a plurality of devices within and/or on a substrate and patterning trenches in an inter-layer dielectric layer on the substrate adjacent the devices. The patterning forms relatively narrow trenches and relatively wide trenches. The methods then perform an angled implant of a compensating material into the trenches. The angle of the angled implant implants a greater concentration of the compensating material in the regions of the substrate at the bottom of the wider trenches relative to an amount of compensating material implanted in the regions of the substrate at the bottom of the narrower trenches. The methods then deposit a metallic material within the trenches and heat the metallic material to form silicide from the metallic material.

8603881, Dec 10, 2013

Sep 20, 2012

13/623292

Ahmet S. Ozcan - Pleasantville NY, US
Viraj Y. Sardesai - Poughkeepsie NY, US
Cung D. Tran - Newburgh NY, US

International Business Machines Corporation - Armonk NY

H01L 21/336

438300, 438 62, 438630, 438648, 438649, 257E21409

A contact via hole is formed through at least one dielectric layer over a semiconductor substrate. A semiconductor material is deposited at the bottom of the contact via hole and atop the at least one dielectric layer by ion cluster deposition. An angled oxygen cluster deposition is performed to convert portions of the semiconductor material on the top surface of the at least one dielectric layer into a semiconductor oxide, while oxygen is not implanted into the deposited semiconductor material at the bottom of the contact via hole. A metal semiconductor alloy is formed at the bottom of the contact hole by deposition of a metal and an anneal. The semiconductor oxide at the top of the at least one dielectric layer can be removed during a preclean before metal deposition, a postclean after metal semiconductor alloy formation, and/or during planarization for forming contact via structures.

8603915, Dec 10, 2013

Nov 28, 2011

13/305122

Emre Alptekin - Wappingers Falls NY, US
Ahmet S. Ozcan - Pleasantville NY, US
Viraj Y. Sardesai - Poughkeepsie NY, US
Cung D. Tran - Newburgh NY, US

International Business Machines Corporation - Armonk NY

H01L 21/44

438674, 438682, 438664

A multi-stage silicidation process is described wherein a dielectric etch to expose contact regions is timed to be optimal for a highest of the contact regions. After exposing the highest of the contact regions, a silicide is formed on the exposed contact region and the dielectric is re-etched, selective to the formed silicide, to expose another contact region, lower than the highest of the contact regions, without recessing the highest of the contact regions. The process then forms a silicide on the lower contact region. The process may continue to varying depths. Each subsequent etch is performed without the use of additional masking steps. By manipulating diffusive properties of existing silicides and deposited metals, the silicides formed on contact regions with differing depths/height may comprise different compositions and be optimized for different polarity devices such as nFET and pFET devices.

8643122, Feb 4, 2014

Dec 6, 2012

13/707058

Viraj Y. Sardesai - Hopewell Junction NY, US
Cung D. Tran - Newburgh NY, US
Jian Yu - Danbury CT, US
Reinaldo A. Vega - Wappingers Falls NY, US
Rajasekhar Venigalla - Hopewell Junction NY, US

International Business Machines Corporation - Armonk NY

H01L 29/417
H01L 29/45
H01L 29/772

257408, 257E29116, 257E29271

A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.

2009017, Jul 9, 2009

Jan 7, 2008

11/970165

Jeffery B. Maxson - New Windsor NY, US
Cung Do Tran - Newburgh NY, US
Huilong Zhu - Poughkeepsie NY, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

H01L 29/78
H01L 21/4763

257384, 438643, 257E29255, 257E21495

The semiconductor structure is provided that has entirely self-aligned metallic contacts. The semiconductor structure includes at least one field effect transistor located on a surface of a semiconductor substrate. The at least one field effect transistor includes a gate conductor stack comprising a lower layer of polysilicon and an upper layer of a first metal semiconductor alloy, the gate conductor stack having sidewalls that include at least one spacer. The structure further includes a second metal semiconductor alloy layer located within the semiconductor substrate at a footprint of the at least one spacer. The structure also includes a first metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the first metal semiconductor alloy layer and a second metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the second metal semiconductor alloy layer.