Curt G Berg, 69San Francisco, CA

6044087, Mar 28, 2000

Jun 30, 1997

8/884971

Shimon Muller - Sunnyvale CA
Curt Berg - Los Altos CA

Sun Microsystems, Inc. - Mountain View CA

H04L 1200

370463

The present invention provides a media-independent interface (MII) on a highly integrated network component by implementing the MII interface with a lower pin count, while reducing the timing budget. In another embodiment, the present invention functions to interface MII compatible devices while reducing pin count and the timing budget.

6061362, May 9, 2000

Jun 2, 1999

9/324875

Shimon Muller - Sunnyvale CA
Curt Berg - Los Altos CA

Sun Microsystems, Inc. - Mountain View CA

H04J 317

370463

The present invention provides a media-independent interface (MII) on a highly integrated network component by implementing the MII interface with a lower pin count, while reducing the timing budget. In another embodiment, the present invention functions to interface MII compatible devices while reducing pin count and the timing budget.

6119196, Sep 12, 2000

Jun 30, 1997

8/884764

Shimon Muller - Sunnyvale CA
Binh Pham - Castro Valley CA
Curt Berg - Los Altos CA

Sun Microsystems, Inc. - Mountain View CA

G06F 1300

710243

A method and apparatus for managing a buffer memory in a packet switch that is shared between multiple ports in a network system. The apparatus comprises a plurality of slow data port interfaces configured to transmit data at a first data rate between a slow data port and the buffer memory and a plurality of fast data port interfaces configured to transmit data at a second data rate between a fast data port and the buffer memory. A first level arbiter is coupled to the plurality of slow data port interfaces. The first level arbiter chooses an access request of one the slow data ports and outputs the access request. A second level arbiter is coupled to the plurality of fast data port interfaces and to the output of the first level arbiter. The second level arbiter chooses an access request from among a plurality access requests from the fast data port interfaces and the access request from the first level arbiter, and forwards the chosen access request to the memory.

6052738, Apr 18, 2000

Jun 30, 1997

8/885154

Shimon Muller - Sunnyvale CA
Binh Pham - Castro Valley CA
Curt Berg - Los Altos CA

Sun Microsystems, Inc.

G06F 1338
G06F 1517

709250

A method and apparatus for controlling access to a shared memory in a network system is described. The apparatus includes at least one fast port interface circuit, each comprising a fast input port interface configured to sequentially receive data, address, and command information from a network client at a first data rate in segments of a first width. Each fast input port interface comprises a fast interface register configured to temporarily store the data and address information. Each fast input port interface further comprises a command decode circuit configured to receive the command information and, in response, sequentially store the segments of data and address information in the fast interface register until the fast interface register is full, the fast interface register further configured to be read out in parallel to the shared memory. The apparatus also includes at least one slow port interface circuit, each configured to receive data, address, and command information from a network client at a second data rate in segments of the first width and transmit the data, address, and command information to a storage circuit that is shared among the slow port interface circuits. The shared storage circuit comprises a plurality of slow interface registers, wherein the segments of data are sequentially stored in one of the slow interface registers at the same time the contents of another slow interface register are read out in parallel to the shared memory.

6023471, Feb 8, 2000

Feb 27, 1998

9/032306

Stephen R. Haddock - Los Gatos CA
Herb Schneider - San Jose CA
Curt Berg - Los Altos CA
Daniel J. Cimino - Oak Park CA
Siddharth Khattar - Goleta CA
Matthew T. Knudstrup - Oak Park CA
Mark Thomas Lytwyn - Redondo Beach CA
Aaron C. Tyler - Thousand Oaks CA
Michael Yip - Sunnyvale CA

Extreme Networks - Santa Clara CA

H04L 1256

370426

A network interconnect device and message exchange protocol for forwarding data among packet forwarding devices are provided. According to one aspect of the present invention, data is forwarded between a first and second packet forwarding device coupled to an interconnect device. The interconnect device receives a menu message from the first packet forwarding device that indicates one or more types of data that are awaiting transmission on the first packet forwarding device. Based upon the menu message, the interconnect device transmits an order message selecting a type of data of the one or more types of data awaiting transmission to the first packet forwarding device. The interconnect device receives a message from the first packet forwarding device containing data of the type selected by the order message. The interconnect device then forwards the data to the second packet forwarding device. According to another aspect of the present invention, data is forwarded among multiple packet forwarding devices through an interconnect device by selecting a configuration of the interconnect device based upon ports to which the packet forwarding devices have data to transfer.

5377345, Dec 27, 1994

Apr 13, 1994

8/227188

Curt Berg - Sunnyvale CA
Jorge Cruz-Rios - San Jose CA

Sun Microsystems, Inc. - Mountain View CA

G06F 1208

395425

Apparatus and methods for a cache controller preserving cache consistency and providing multiple outstanding operations in a cache memory structure supporting a high performance central processor unit (CPU). An external cache array is coupled to both the CPU and a cache controller (CC), and is subblocked to reduce miss rate. The CC is coupled via a high speed bus to a main memory. A cache directory in the CC tracks usage of the external cache, and is organized to support a choice of bus protocols for buses intercoupling the CC to the main memory. The cache directory consists of tag entries, each tag entry having an address field and multiple status bit fields, one status bit field for each subblock. The status bit fields, in addition to shared-, owner-, and valid-bits, have a pending-bit which, when set, indicates a pending uncompleted outstanding operation on a subblock, and will prevent the CPU from overwriting the corresponding subblock. Two block miss registers in the CPU aid in prefetching subsequent subblocks upon subblock miss.

6021132, Feb 1, 2000

Dec 9, 1997

8/987914

Shimon Muller - Sunnyvale CA
Ariel Hendel - Cupertino CA
Ravi Tangirala - Mountain View CA
Curt Berg - Los Altos CA

Sun Microsystems, Inc. - Mountain View CA

H04L 1246

370412

A method and apparatus for shared memory management in a switched network element is provided. According to one aspect of the present invention, a shared memory manager for a packet forwarding device includes a pointer memory having stored therein information regarding buffer usage (e. g. , usage counts) for each of a number of buffers in a shared memory. An encoder is coupled to the pointer memory for generating an output which indicates a set of buffers that contains a free buffer. The shared memory manager further includes a pointer generator that is coupled to the encoder for locating a free buffer in the set of buffers. The pointer generator is further configured to produce a pointer to the free buffer based upon the output of the encoder and the free buffer's location within the set of buffers. According to another aspect of the present invention, a packet forwarding device includes a number of output ports for transmitting packets onto a network and a number of input ports coupled to the output ports for receiving packets from the network, buffering the packets, and forwarding the packets to one or more of the output ports. The packet forwarding device also includes a shared memory that is segmented into buffers for temporarily buffering the packets.

5398325, Mar 14, 1995

May 7, 1992

7/879611

Curt Berg - Sunnyvale CA
Jorge Cruz-Rios - San Jose CA

Sun Microsystems, Inc. - Mountain View CA

G06F 1202

395425

Apparatus and methods for a cache controller to maintain cache consistency in a cache memory structure having a single copy of a cache tag memory while supporting multiple outstanding operations in a multiple processor computer system. The CPU includes a small internal cache memory structure. A substantially larger external cache array is coupled to both the CPU and the CC via first, integrated address and data bus. The CC is in turn coupled to a second bus interconnecting, among other devices, processors, I/O devices, and a main memory. The external cache is subblocked. A cache directory in the CC tracks usage of the external cache. An input buffer in the CC is connected to the first bus to provide buffering of commands sent by the CPUs. An output buffer in the CC is coupled to the second bus for buffering commands directed by the CC to devices operating on the second bus. A virtual bus interface (VBI) receives entries made in the input buffer, whereafter the input buffer is relieved to accept other commands.