Dale Carol K Adams, 703040 Kanu St, Honolulu, HI 96822

6380978, Apr 30, 2002

Oct 6, 1998

09/167527

Dale R. Adams - San Jose CA
Laurence A. Thompson - Saratoga CA
Jano D. Banks - Cupertino CA
David C. Buuck - Santa Clara CA
Cheng Hwee Chee - Saratoga CA

DVDO, Inc. - Campbell CA

H04N 701

348452, 348448

A digital image enhancer includes a deinterlacing processor receptive to an interlaced video stream. The deinterlacing processor includes a first deinterlacer and a second deinterlacer and provides a deinterlaced video stream. The digital image enhancer also includes a video output processor receptive to the output of the deinterlaced video stream to provide a scaled, deinterlaced video stream. A portable DVD player including the digital video enhancer has a generally thin prismatic enclosure having a first major surface, a second major surface separated from said first major surface, and side surfaces connecting the first major surface to the second major surface. At least a portion of the first major surface includes a video display, and the enclosure includes a DVD entry port such that a DVD can be inserted into the enclosure.

6385692, May 7, 2002

Mar 12, 2001

09/805588

Jano D. Banks - Cupertino CA
Dale R. Adams - San Jose CA
Albert M. Scalise - San Jose CA

Silicon Image, Inc. - Sunnyvale CA

G06F 1200

711105, 711 5, 711158

Disclosed is a SDRAM system including a SDRAM having multiple banks of memory, a plurality of bank state machines associated the multiple banks of memory of the SDRAM, and a data control state machine. The data state machine is responsive to a memory request for a variable length data transfer with the SDRAM and as well as the bank state machines. The data control state machine determines the current state of a first bank of memory of the SDRAM. The current state may be either a read in progress, a write in progress, or idle. The data control state machine then handles the memory request with a different bank of memory RAM depending upon the current state of the first bank of memory.

6489998, Dec 3, 2002

Aug 11, 1999

09/372713

Laurence A. Thompson - Saratoga CA
Dale R. Adams - San Jose CA

DVDO, Inc. - Campbell CA

H04N 1100

348452, 348448

A digital image processor is provided. The digital image processor includes a deinterlacing processor that is implemented upon a digital processing unit. The deinterlacing processor is coupled to an input operable to receive an interlaced video stream, a digital memory for storing portions of the interlaced video signal, and an output operable to transmit a deinterlaced video stream. The deinterlacing processor is operable to perform frequency analysis upon the received interlaced video stream in order to generate the deinterlaced video stream having reduced motion artifacts.

6515706, Feb 4, 2003

Sep 15, 1999

09/396993

Laurence A. Thompson - Saratoga CA
Dale R. Adams - San Jose CA

DVDO, Inc. - Campbell CA

H04N 701

348448, 348452

A digital image processor is provided. The digital image processor includes a deinterlacing processor coupled between an input buffer operable to receive an interlaced video stream and an output operable to transmit a deinterlaced video stream. The deinterlacing processor is also coupled to a digital memory for storing portions of the interlaced video signal. The deinterlacing processor is operable to detect said diagonal features in the portions of the received interlaced video stream and to generate the deinterlaced video stream having smoothed diagonal features.

6587158, Jul 1, 2003

Jul 22, 1999

09/359530

Dale R. Adams - San Jose CA
Laurence A. Thompson - Saratoga CA
Jano D. Banks - Cupertino CA

DVDO, Inc. - Campbell CA

H04N 964

348716, 348715, 348714, 348206, 345543, 345545, 345547

A digital image processor includes an input buffer for storing raster-scanned data. A slice-buffer memory is coupled to the input buffer to store a portion of a vertical slice of said raster-scanned data. The vertical slice is processed by a vertical slice processor having an input coupled to the slice-buffer memory. The vertical slice processor reassembles the vertical slices into processed raster-scanned data in an output buffer that is coupled to the output of the vertical slice processor. The digital image processor preferably utilizes multiple sequential processing stages and processes the raster-scanned data along the horizontal axis of the vertical slices.

6700622, Mar 2, 2004

Oct 1, 1999

09/410543

Dale R. Adams - San Jose CA
Laurence A. Thompson - Saratoga CA

DVDO, Inc. - Campbell CA

H04N 701

348448, 348452

A digital image processor is provided. The digital image processor includes a deinterlacing processor that is implemented upon a digital processing unit. The deinterlacing processor is coupled to an input operable to receive an interlaced video stream, a digital memory for storing portions of the interlaced video signal, and an output operable to transmit a deinterlaced video stream. The deinterlacing processor is operable to detect the source type of the received interlaced video stream to generate the deinterlaced video stream having reduced or no motion artifacts.

6714206, Mar 30, 2004

Dec 10, 2001

10/016247

Russel A. Martin - Menlo Park CA
Dale Adams - San Jose CA
Duane Siemens - Mountain View CA
Hugo Steemers - Mountain View CA

Silicon Image - Sunnyvale CA

G09G 502

345589, 345596, 345605, 345597, 345600, 345690, 345694, 345695, 358518, 358519, 358520

A method and system for establishing intensity levels for sub-pixels of a display device with overlapping logical pixels. The dithering system combines frame rate control techniques with contributions from overlapping pixels to establish the intensity level of each sub-pixel. The dithering system initially provides an assignment of frame numbers to each sub-pixel. The dithering system then receives a logical pixel color that includes an intensity value for each component color (e. g. , red, green, and blue) for each logical pixel. The dithering system maps each component intensity value of each logical pixel to an intensity value with a low depth plus a remainder. The dithering system generates a sub-pixel intensity value for each sub-pixel of each logical pixel using frame rate control to adjust the intensity value of each sub-pixel based on the remainder and current frame number. The dithering system then calculates the intensity value for a sub-pixel by combining all the generated sub-pixel intensity values for that sub-pixel.

6829013, Dec 7, 2004

Jul 8, 2002

10/191764

Laurence A. Thompson - Saratoga CA
Dale R. Adams - San Jose CA

Silicon Image, Inc. - Sunnyvale CA

H04N 701

348448, 348452

A digital image processor includes an input buffer operable to receive an interlaced video stream and a digital memory for storing portions of the interlaced video stream. An output buffer is operable to transmit a deinterlaced video stream. Also included is a deinterlacing processor coupled between said input buffer and said output buffer and to said digital memory, said deinterlacing processor is operable to store portions of said received interlaced video stream from said input buffer into said digital memory and to detect diagonal features in said portions of said received interlaced video stream in said digital memory, and to generate said deinterlaced video stream having smoothed diagonal features therefrom.