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Daniel Martin Bax, 421860 Fuller Ave, Los Angeles, CA 90046

Daniel Bax Phones & Addresses

1860 Fuller Ave, Los Angeles, CA 90046   

1215 Sycamore St, Los Angeles, CA 90038   

West Hollywood, CA   

Marina del Rey, CA   

Portland, OR   

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Daniel Bax resumes & CV records

Resumes

Daniel Bax Photo 34

Producer - Audio Engineer - Musician - Artist

Location:
Greater Los Angeles Area
Industry:
Entertainment
Daniel Bax Photo 35

Owner - Chief Executive Officer - Producer - Consultant - Artist

Location:
Los Angeles, CA
Industry:
Entertainment
Work:
Bax Images
Owner - Professional Photographer and Videographer
Bax Volleyball Jan 2001 - Jan 2012
Owner
Bax Trax Entertainment Jan 2001 - Jan 2012
Owner - Chief Executive Officer - Producer - Consultant - Artist
Skills:
Entertainment, Film, Music Production, Post Production, Recording, Video Production, Sound Design, Television, Music, Film Production, Multimedia, Social Media, Video Editing, Videography, Photography, Social Media Marketing, Audio Editing, Sound, Video, Social Networking, Customer Service, Advertising, Marketing, Hd Video, Event Planning, Editing, Mastering, Graphic Design, Guitar, Commercials, Photoshop, Event Management, Digital Media, Marketing Strategy, Audio Engineering, Music Industry, Final Cut Pro, Live Events, New Media, Leadership, Composition, Creative Direction, Studio Recording, Songwriting
Languages:
Spanish
Daniel Bax Photo 36

Daniel Bax

Publications & IP owners

Us Patents

Service Processor Access Of Non-Volatile Memory

US Patent:
6701403, Mar 2, 2004
Filed:
Oct 1, 2001
Appl. No.:
09/969262
Inventors:
Richard A. Lary - Tualatin OR
Daniel H. Bax - Portland OR
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1200
US Classification:
710305, 711103, 711163, 710306, 710311, 710312, 710313, 36523002
Abstract:
Non-volatile memory access, such as firmware access by a service processor, is disclosed. The service processor asserts a controller signal to select either a first non-volatile memory, or a second non-volatile memory. The first non-volatile memory is located behind a first bridge controller and is otherwise accessible by the service processor. The second non-volatile memory is located behind a second bridge controller and is otherwise accessible only by a processor other than the service processor. The service processor then access the selected non-volatile memory, via a bus communicatively coupled to both the non-volatile memories.

Aggregation Of Hardware Events In Multi-Node Systems

US Patent:
6988155, Jan 17, 2006
Filed:
Oct 1, 2001
Appl. No.:
09/968768
Inventors:
Richard A. Lary - Tualatin OR, US
Daniel H. Bax - Portland OR, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 13/24
US Classification:
710260, 710266
Abstract:
The aggregation of hardware events in multi-node systems is disclosed. An event occurring at a remote node is forwarded to a primary node, by firmware of the remote node writing to a first register of the primary node. The event is propagated from the first register of the primary node to a second register node. In automatic response, an interrupt is generated at the primary node. An interrupt handler of the primary node, in response to generation of the interrupt, then invokes code at the primary node to handle the event occurring at the remote node.

Fabric-Backplane Enterprise Servers With Pluggable I/O Sub-System

US Patent:
2013011, May 9, 2013
Filed:
Apr 17, 2007
Appl. No.:
11/736355
Inventors:
Daniel H. Bax - Portland OR, US
Russell M. Clapp - Portland OR, US
Tom Gourley - Banks OR, US
Geoffrey H. Hanson - Sunnyvale CA, US
Allen Hirashiki - San Ramon CA, US
Thomas Dean Lovett - Portland OR, US
Sharad Mehrotra - Saratoga CA, US
Shyam Mittur - Los Gatos CA, US
Nakul Pratap Saraiya - Palo Alto CA, US
International Classification:
G06F 3/00
US Classification:
719323
Abstract:
A Cost-Reduced Enterprise Server (CRES) system includes a flexible resource-efficient server having a plurality of Processor Memory Boards (PMBs) coupled to an Input/Output Module (IOM). The IOM provides all networking and storage interfaces for the server. The IOM is implemented as a field-replaceable pluggable module, and thus all Input/Output (I/O) capabilities or resources of a CRES system may be upgraded via replacement of the IOM. Each PMB is dividable into a pair of Symmetric MultiProcessor (SMP) complexes, and each complex is coupled to a respective portion of the I/O resources provided by the IOM. Each portion of the IOM provides a pair of I/O daughter-module connectors compatible with standard I/O interfaces, such as Peripheral Component Interconnect (PCI)-X and PCI-Express. One or more CRES systems may be coupled to one or more Enterprise Server (ES) systems to form a multi-chassis server managed collectively as one or more provisioned servers.

Voltage Protection For Computer Processors

US Patent:
6445556, Sep 3, 2002
Filed:
May 23, 2000
Appl. No.:
09/577237
Inventors:
Daniel H. Bax - Aloha OR
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H02H 900
US Classification:
361 911, 361 90, 361 78, 361 18
Abstract:
A multi processor computer system includes processors in processor receptacles , and voltage modules and voltage module receptacle. The system accepts both direct voltage processors powered directly from the system power plane, and regulated voltage processors which require a voltage regulator. The regulated voltage processors require the voltage regulator while the direct voltage processors cannot operate with a voltage regulator. Voltage module control circuit tests and compares processor type signals from the processor receptacles and voltage module type signals from the voltage module receptacles, and produces a voltage validation signal which indicates the presence of a mismatch between any of the processors and its respective voltage module. The voltage validation signal modifies the conventional processor presence signal from the processor receptacles if a mismatch exists, preventing the system from being powered on.

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