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Daniel W Bedell, 49Goshen, VT

Daniel Bedell Phones & Addresses

Brandon, VT   

7566 Edinburgh Way, Gilroy, CA 95020    408-8469776   

358 La Strada Dr, San Jose, CA 95123    408-2271923   

376 La Strada Dr, San Jose, CA 95123    408-2271923   

Orem, UT   

Provo, UT   

Hinesburg, VT   

358 La Strada Dr APT 16, San Jose, CA 95123    408-9107040   

Work

Company: Piatnicia legal Oct 2012 Position: Special counsel

Education

School / High School: Santa Clara University School of Law- Santa Clara, CA 2003 Specialities: J.D.

Skills

Conversant in Spanish

Ranks

Licence: California - Active Date: 2008

Mentions for Daniel W Bedell

Career records & work history

Lawyers & Attorneys

Daniel Bedell Photo 1

Daniel Wayne Bedell, San Jose CA - Lawyer

Address:
5339 Prospect Rd., No. 194, San Jose, CA 95129
408-6411797 (Office)
Licenses:
California - Active 2008
Experience:
Attorney at Piatnicia Legal - 2012-present
Attorney at The Lanier Law Firm - 2008-2012
Associate at Howrey - 2006-2008
Lithography Engineer at Hitachi Global Storage Technologies - 2003-2006
Lithography Engineer at IBM - 1999-2003
Education:
Santa Clara Univ SOLDegree JD - Juris Doctor - LawGraduated 2007
Brigham Young UniversityDegree BS - Bachelor of Science - Chemical EngineeringGraduated 1999
Specialties:
Intellectual Property - 100%
Languages:
English, Spanish
Daniel Bedell Photo 2

Daniel Bedell - Lawyer

Specialties:
Intellectual Property
ISLN:
919644845
Admitted:
2008
University:
Brigham Young University, B.A., 1999
Law School:
Santa Clara University School of Law, J.D., 2007

Daniel Bedell resumes & CV records

Resumes

Daniel Bedell Photo 48

Counsel, Intellectual Property At Agilent Technologies

Location:
6765 Eagle Ridge Ct, Gilroy, CA 95020
Industry:
Biotechnology
Work:
Agilent Technologies
Counsel, Intellectual Property at Agilent Technologies
Amin, Turocy & Watson, Llp
Partner
Piatnicia Legal Oct 2012 - Sep 2013
Special Counsel
The Lanier Law Firm Jun 2008 - Sep 2012
Associate
Howrey Llp May 2006 - Jun 2008
Associate
Ibm Aug 1999 - May 2006
Engineer
Education:
Santa Clara University School of Law 2016 - 2020
Doctor of Jurisprudence, Doctorates
Santa Clara University 2007
Doctor of Jurisprudence, Doctorates
Santa Clara University School of Law 2004 - 2007
Doctor of Jurisprudence, Doctorates
Brigham Young University 1994 - 1999
Bachelors, Bachelor of Science, Chemical Engineering
Skills:
Patents, Patent Litigation, Intellectual Property, Patent Prosecution, Litigation, Licensing, Trademarks, Trade Secrets, Trademark Infringement, Registered Patent Attorney, Trials, Patent Applications, Legal Writing, Semiconductors, Unfair Competition, Appeals, Courts, Civil Litigation, Commercial Litigation, Negotiation, Research, Management, Thin Films, Privacy Law
Interests:
Hiking
Woodworking
Mountain Biking
Languages:
English
Spanish
Daniel Bedell Photo 49

Associate

Location:
San Francisco, CA
Industry:
Law Practice
Work:
Howrey Llp
Associate
Daniel Bedell Photo 50

Engineer

Work:
Dod
Engineer
Daniel Bedell Photo 51

Daniel Bedell

Daniel Bedell Photo 52

Daniel Bedell

Skills:
Microsoft Excel, Management, Microsoft Word, Microsoft Office
Daniel Bedell Photo 53

Daniel Bedell

Location:
United States
Daniel Bedell Photo 54

Daniel Bedell

Location:
United States
Daniel Bedell Photo 55

Daniel Bedell

Location:
United States

Publications & IP owners

Us Patents

Method For Patterning A Self-Aligned Coil Using A Damascene Process

US Patent:
7022248, Apr 4, 2006
Filed:
Aug 29, 2003
Appl. No.:
10/652878
Inventors:
Daniel Wayne Bedell - San Jose CA, US
Quang Le - San Jose CA, US
Edward Hin Pong Lee - San Jose CA, US
Son Van Nguyen - Los Gatos CA, US
Vladimir Nikitin - Campbell CA, US
Murali Ramasubramanian - San Jose CA, US
Assignee:
Hitachi Global Storage Technologies Netherlands B.V.
International Classification:
B44C 1/22
US Classification:
216 22, 216 13, 216 17, 216 18, 216 88, 216 89, 2960301
Abstract:
A method for patterning a self-aligned coil using a damascene process is disclosed. Coil pockets are formed in a first insulation layer disposed over a first pole layer. A barrier/seed layer is deposited along walls of the coil pockets in the insulation layer. Copper is formed in the coil pockets and over the insulation layer. The copper is planarized down to the insulation layer. The self-aligned coil process packs more copper into the same coil pocket and relaxes the coil alignment tolerance. Protrusions are prevented because of the more efficient and uniform spacing of the coil to reduce heat buildup in the head during a write.

Apparatus For Patterning A Self-Aligned Coil Using A Damascene Process

US Patent:
7075750, Jul 11, 2006
Filed:
Aug 29, 2003
Appl. No.:
10/652877
Inventors:
Daniel Wayne Bedell - San Jose CA, US
Quang Le - San Jose CA, US
Edward Hin Pong Lee - San Jose CA, US
Son Van Nguyen - Los Gatos CA, US
Vladimir Nikitin - Campbell CA, US
Murali Ramasubramanian - San Jose CA, US
Assignee:
Hitachi Global Storage Technologies Netherlands B.V. - Amsterdam
International Classification:
G11B 5/147
US Classification:
360126, 360123
Abstract:
An apparatus for patterning a self-aligned coil using a damascene process is disclosed. Coil pockets are formed in a first insulation layer disposed over a first pole layer. A barrier/seed layer is deposited along walls of the coil pockets in the insulation layer. Copper is formed in the coil pockets and over the insulation layer. The copper is planarized down to the insulation layer. The self-aligned coil process packs more copper into the same coil pocket and relaxes the coil alignment tolerance. Protrusions are prevented because of the more efficient and uniform spacing of the coil to reduce heat buildup in the head during a write.

Method For Reducing Pole Height Loss In The Formation Of A Write Pole For A Magnetic Write Head

US Patent:
7263762, Sep 4, 2007
Filed:
Sep 30, 2004
Appl. No.:
10/957038
Inventors:
Daniel Bedell - Gilroy CA, US
Jennifer A. Loo - Gilroy CA, US
Aron Pentek - San Jose CA, US
Murali Ramasubramanian - Fremont CA, US
Assignee:
Hitachi Global Storage Technologies - San Jose CA
International Classification:
G11B 5/127
G11B 5/187
US Classification:
2960301, 2960312, 2960313, 2960314, 2960315, 2960316, 2960318, 360122
Abstract:
A method for reducing plated pole height loss in the formation of a write pole for a magnetic write head is disclosed. The method includes forming a conductive layer on a thin film substrate, forming a photoresist layer on the conductive layer and forming a trench in the photoresist layer. A thick seed layer is then placed on the trench and on the photoresist layer surface using a collimator. Moreover, the process includes plating while applying a voltage to the thin film substrate where the electrically isolated seed layer is removed and the trench is filled with plating material, removing the photoresist layer, and removing the exposed portions of the conductive layer on the thin film substrate.

Process For Creating A Write Head By Forming A Bump After The Top Pole Is Formed

US Patent:
7363698, Apr 29, 2008
Filed:
Sep 30, 2004
Appl. No.:
10/956221
Inventors:
Amanda Baer - Campbell CA, US
Hamid Balamane - Palo Alto CA, US
Daniel Wayne Bedell - Gilroy CA, US
Jyh-Shuey Jerry Lo - San Jose CA, US
Vladimir Nikitin - Campbell CA, US
Aron Pentek - San Jose CA, US
Yvette Winton - San Francisco CA, US
Assignee:
Hitachi Gobal Storage Technologies Inc.
International Classification:
G11B 5/127
H04R 31/00
US Classification:
2960316, 2960313, 2960315, 2960318, 216 22, 216 26, 360122, 360126, 360317, 451 5, 451 41
Abstract:
Methods for creating a write head by forming a bump after the top pole is formed are provided. In one embodiment, a bottom pole is created out of a first layer. A non-magnetic gap material is applied to the surface of the wafer. A top pole is created out of a second layer. After creating the top pole, a bump is created. The bump is used to protect at least a portion of the first layer while etching to create a stray flux absorber.

Method For Making Magnetic Write Head

US Patent:
7380330, Jun 3, 2008
Filed:
Jul 21, 2005
Appl. No.:
11/186174
Inventors:
Daniel Wayne Bedell - Gilroy CA, US
Aron Pentek - San Jose CA, US
Katalin Pentek - San Jose CA, US
Yi Zheng - San Ramon CA, US
Assignee:
Hitachi Global Storage Technologies Netherlands B.V. - Amsterdam
International Classification:
G11B 5/127
US Classification:
2960312, 2960307, 2960313, 2960315, 2960318
Abstract:
After defining the P2 pole of a magnetic read head, alumina is deposited over it and planarized by CMP, with the portion of the alumina overlaying the ABS region of the P2 pole subsequently being masked by a photoresist layer and with the portions of the alumina overlaying the flare area, back gap region, and center tap regions of the P2 pole not being masked. A reactive ion mill is performed to expose the flare area, back gap region, and center tap regions of the P2 pole by removing the alumina over these portions, so that subsequent steps such as forming a layer of coiled conductors, forming a return pole, and forming stud connections along with removing the respective seed layers can be executed with the ABS region protected by the alumina and with the flare area, back gap region, and center tap region exposed.

Magnetic Head Coil System And Damascene/Reactive Ion Etching Method For Manufacturing The Same

US Patent:
7380332, Jun 3, 2008
Filed:
Jan 20, 2005
Appl. No.:
11/040387
Inventors:
Daniel Wayne Bedell - San Jose CA, US
Richard Hsiao - San Jose CA, US
James D. Jarratt - Schenectady NY, US
Patrick Rush Webb - Los Gatos CA, US
Sue Siyang Zhang - Saratoga CA, US
Assignee:
Hitachi Global Storage Technologies Netherlands B.V. - Amsterdam
International Classification:
G11B 5/17
US Classification:
2960325, 2960323, 29606, 216 39
Abstract:
A system and method are provided for manufacturing a coil structure for a magnetic head. Initially, an insulating layer is deposited with a photoresist layer deposited on the insulating layer. Moreover, a silicon dielectric layer is deposited on the photoresist layer as a hard mask. The silicon dielectric layer is then masked. A plurality of channels is subsequently formed in the silicon dielectric layer using reactive ion etching (i. e. CF/CHF). The silicon dielectric layer is then used as a hard mask to transfer the channel pattern in the photoresist layer using reactive ion etching with, for example, H/N/CHF/CHreducing chemistry. To obtain an optimal channel profile with the desired high aspect ratio, channel formation includes a first segment defining a first angle and a second segment defining a second angle. Thereafter, a conductive seed layer is deposited in the channels and the channels are filled with a conductive material to define a coil structure. Chemical-mechanical polishing may then be used to planarize the conductive material.

Magnetic Head Coil System And Damascene/Reactive Ion Etching Method For Manufacturing The Same

US Patent:
7397634, Jul 8, 2008
Filed:
Jun 23, 2003
Appl. No.:
10/602462
Inventors:
Daniel Wayne Bedell - San Jose CA, US
Richard Hsiao - San Jose CA, US
James D. Jarratt - Schenectady NY, US
Patrick Rush Webb - Los Gatos CA, US
Sue Siyang Zhang - Saratoga CA, US
Assignee:
Hitachi Global Storage Technologies Netherlands B.V. - Amsterdam
International Classification:
G11B 5/17
US Classification:
360126, 360317
Abstract:
A system and method are provided for manufacturing a coil structure for a magnetic head. Initially, an insulating layer is deposited with a photoresist layer deposited on the insulating layer. Moreover, a silicon dielectric layer is deposited on the photoresist layer as a hard mask. The silicon dielectric layer is then masked. A plurality of channels is subsequently formed in the silicon dielectric layer using reactive ion etching (i. e. CF/CHF). The silicon dielectric layer is then used as a hard mask to transfer the channel pattern in the photoresist layer using reactive ion etching with, for example, H/N/CHF/CHreducing chemistry. To obtain an optimal channel profile with the desired high aspect ratio, channel formation includes a first segment defining a first angle and a second segment defining a second angle. Thereafter, a conductive seed layer is deposited in the channels and the channels are filled with a conductive material to define a coil structure. Chemical-mechanical polishing may then be used to planarize the conductive material.

Ion Mill Process With Sacrificial Mask Layer To Fabricate Pole Tip For Perpendicular Recording

US Patent:
7506428, Mar 24, 2009
Filed:
Sep 30, 2003
Appl. No.:
10/676728
Inventors:
Daniel Wayne Bedell - San Jose CA, US
Gautam Khera - Morgan Hill CA, US
Quang Le - San Jose CA, US
Aron Pentek - San Jose CA, US
Assignee:
Hitachi Global Storage Technologies Netherlands B.V. - Amsterdam
International Classification:
G11B 5/187
US Classification:
2960312, 2960313, 2960323, 20419234, 360122
Abstract:
A method of fabrication of the write head of a perpendicular recording head allows for production of P pole tips of width less than 200 nm (200×10meters). The method includes fabricating the P flux shaping layer, depositing the P layer, depositing a layer of ion-milling resistant material, depositing at least one sacrificial layer, shaping the P layer into P pole tip, removing the at least one sacrificial layer to leave the P pole tip, and encapsulating the P pole tip.

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