Inventors:
Chenming Hu - Oakland CA, US
Anupama Bowonder - Berkeley CA, US
Pratik Patel - Berkeley CA, US
Daniel Chou - Houston TX, US
Prashant Majhi - Austin TX, US
Assignee:
The Regents of the University of California - Oakland CA
International Classification:
H01L 29/66
US Classification:
257105, 257 30, 257 39, 257104, 257E29024, 257E29168
Abstract:
Several embodiments of a tunneling transistor are disclosed. In one embodiment, a tunneling transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a gate stack including a metallic gate electrode and a gate dielectric, and a tunneling junction that is substantially parallel to an interface between the metallic gate electrode and the gate dielectric. As a result of the tunneling junction that is substantially parallel with the interface between the metallic gate electrode and the gate dielectric, an on-current of the tunneling transistor is substantially improved as compared to that of a conventional tunneling transistor. In another embodiment, a tunneling transistor includes a heterostructure that reduces a turn-on voltage of the tunneling transistor.
