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Daniel J Hadad, 516300 Salcon Cliff Dr, Austin, TX 78749

Daniel Hadad Phones & Addresses

6300 Salcon Cliff Dr, Austin, TX 78749    512-3015498   

5900 Pecanwood Ln, Austin, TX 78749    512-3015498   

3356 Lake Austin Blvd, Austin, TX 78703    512-4783833   

Eufaula, OK   

San Antonio, TX   

Houston, TX   

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Daniel J Hadad

Linkedin

Work

Company: Nxp semiconductors Dec 2015 Position: Principal nvm test engineer

Education

Degree: Masters, Master of Science In Electrical Engineering School / High School: The University of Texas at Austin 1995 to 1997 Specialities: Physics

Skills

Semiconductors • Electrical Engineering • Dft • Yield • Device Characterization • Ic • Product Engineering • Spice • Jmp • Hardware Architecture • Debugging • Rtl Design • Silicon • Microcontrollers • Characterization • Embedded Systems • Perl • Ruby • Test Engineering • Testing • Mixed Signal • Cmos • Verilog • Analog • Electronics • Soc • Embedded Software • Semiconductor Industry • C++ • System on A Chip • Integrated Circuits

Languages

English • Spanish • Italian • French

Ranks

Certificate: Edx Verified Certificate For Embedded Systems - Shape the World

Interests

Science and Technology • Education

Emails

Industries

Semiconductors

Mentions for Daniel J Hadad

Daniel Hadad resumes & CV records

Resumes

Daniel Hadad Photo 35

Principal Nvm Test Engineer

Location:
Austin, TX
Industry:
Semiconductors
Work:
Nxp Semiconductors
Principal Nvm Test Engineer
Freescale Semiconductor Apr 2004 - Dec 2015
Nvm Senior Test Engineer - Member Technical Staff
Freescale Semiconductor Dec 2000 - Apr 2004
Nvm Senior Test Engineer
Freescale Semiconductor Aug 1997 - Dec 2000
Characterization and Modeling Engineer
Education:
The University of Texas at Austin 1995 - 1997
Masters, Master of Science In Electrical Engineering, Physics
Trinity University 1991 - 1995
Bachelor of Science In Engineering, Bachelors, Electrical Engineering
Skills:
Semiconductors, Electrical Engineering, Dft, Yield, Device Characterization, Ic, Product Engineering, Spice, Jmp, Hardware Architecture, Debugging, Rtl Design, Silicon, Microcontrollers, Characterization, Embedded Systems, Perl, Ruby, Test Engineering, Testing, Mixed Signal, Cmos, Verilog, Analog, Electronics, Soc, Embedded Software, Semiconductor Industry, C++, System on A Chip, Integrated Circuits
Interests:
Science and Technology
Education
Languages:
English
Spanish
Italian
French
Certifications:
Edx Verified Certificate For Embedded Systems - Shape the World
Utaustinx Ut.rtbd.12.01X: Realtime Bluetooth Networks

Publications & IP owners

Wikipedia

Daniel Hadad Photo 36

Daniel Hadad

Daniel Hadad (born November 28, 1961) is an Argentine businessman involved in telecommunications and media. Life and times. Daniel Hadad was born in Buenos

Us Patents

Non-Volatile Memory (Nvm) With Imminent Error Prediction

US Patent:
8572445, Oct 29, 2013
Filed:
Sep 21, 2010
Appl. No.:
12/886861
Inventors:
Richard K. Eguchi - Austin TX, US
Daniel Hadad - Austin TX, US
Chen He - Austin TX, US
Katrina M. Prosperi - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G11C 29/00
US Classification:
714721, 365200, 365201
Abstract:
A method and system are provided for determining an imminent failure of a non-volatile memory array. The method includes: performing a first array integrity read of the memory array until an error is detected; determining that the error is not error correction code (ECC) correctable, wherein a first word line voltage associated with the error is characterized as being a first threshold voltage; performing a second array integrity read of the memory array until all bits of the memory array indicate a predetermined state, wherein a second word line voltage associated with all of the bits indicating the predetermined state is a second threshold voltage; and comparing a difference between the first and second threshold voltages to a predetermined value.

Method And Apparatus For Eeprom Emulation For Preventing Data Loss In The Event Of A Flash Block Failure

US Patent:
2012013, May 24, 2012
Filed:
Nov 24, 2010
Appl. No.:
12/954130
Inventors:
Chen He - Austin TX, US
Richard K. Eguchi - Austin TX, US
Daniel Hadad - Austin TX, US
Katrina M. Prosperi - Austin TX, US
International Classification:
G06F 12/02
US Classification:
711103, 711E12008
Abstract:
A defect resistant EEPROM emulator () uses one or more redundant and/or spare blocks () in addition to active and alternate blocks () and stores a duplicate copy of EEPROM data records either in the active and redundant blocks or in duplicate rows in the active block to ensure that EEPROM emulation can continue without data loss in the event a catastrophic failure occurs within a block.

Non-Volatile Memory (Nvm) With Imminent Error Prediction

US Patent:
2014004, Feb 6, 2014
Filed:
Oct 8, 2013
Appl. No.:
14/048362
Inventors:
Richard K. Eguchi - Austin TX, US
Daniel Hadad - Austin TX, US
Chen He - Austin TX, US
Katrina M. Prosperi - Austin TX, US
International Classification:
G11C 29/38
US Classification:
714719
Abstract:
A non-volatile memory system includes a memory array and a memory controller. The memory controller is configured to perform a first array integrity read operation of the array until an error is detected. The controller is also configured to determine that the error is not error correction code (ECC) correctable. A first word line voltage associated with the error is characterized as being a first threshold voltage. The controller is further configured to perform a second array integrity read operation of the array. The second array integrity read operation includes reading the array with a word line read voltage that is offset from the first threshold voltage and is based on a predetermined width offset reference value. Finally, the controller is configured to check a check sum value resulting from the second array integrity read operation to determine when an imminent failure in the memory array is indicated.

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