Daniel W Storaska, 5036 Decker Dr, Walden, NY 12586

6438051, Aug 20, 2002

May 31, 2001

09/870559

John A. Fifield - Underhill VT
Wing K. Luk - Chappaqua NY
Daniel W. Storaska - Wappingers Falls NY

International Business Machines Corporation - Armonk NY

G11C 704

365207, 365211, 327 51

A stabilized direct sensing memory architecture which provides Process, Voltage and Temperature (PVT) compensation in a memory array to a direct sense circuit to increase the manufacturing yield thereof, and to extend the operating voltage and temperature ranges thereof independent of manufacturing tolerances. A single-ended sense amplifier structure has a common source NFET amplifier with an adjustable current source load provided by a PFET. The PFET current source is automatically adjusted to place the NFET amplifier in an operating range to provide maximum amplification of a small signal superimposed on a bitline precharge voltage. A mimic bias generator circuit provides this operating point adjustment, and realizes a direct, single-ended sensing operation using a small number of transistors.

6445611, Sep 3, 2002

Sep 28, 2001

09/966142

John A. Fifield - Chittenden VT
Daniel W. Storaska - Walden NY

International Business Machines Corporation - Armonk NY

G11C 1124

365149, 36518901, 36518904, 36523006

An arrangement and method is disclosed which works toward shortening the machine cycle of a DRAM. A data value is written to a storage capacitor of a memory cell of the DRAM, the data value being stored in the storage capacitor as one of low state and high state. During a first wordline activation cycle, a storage capacitor is preconditioned to a preconditioned voltage level. In a subsequent wordline activation cycle, a low state or a high state is written to the storage capacitor. In an aspect of the invention, the wordline is activated in a first wordline activation cycle to begin clearing any previously stored state of the storage capacitor. This cycle may include the reading of a stored data value from the storage capacitor. Then, immediately thereafter, while maintaining the wordline activated, the storage capacitor is preconditioned to a preconditioned voltage level, as by clamping the bitline through a bitline restore device. The wordline is then deactivated.

6449202, Sep 10, 2002

Aug 14, 2001

09/929593

Hiroyuki Akatsu - Yorktown Heights NY
Louis L. Hsu - Fishkill NY
Jeremy K. Stephens - New Windsor NY
Daniel W. Storaska - Walden NY

International Business Machines Corporation - Armonk NY

G11C 700

365205, 365203

A direct sensing circuit and method for reading data from a memory cell connected to a bitline, with open bitline sensing without using a reference bitline signal, onto a data line in a data read operation. Prior to the data read operation, both the bitline and the data line are precharged to precharge voltages and a sense node is precharged to ground. A pFET device has its gate coupled to a signal developed on the bitline from the memory cell to detect and amplify the signal level thereof, and has its source coupled to a voltage source and its drain coupled to a sense node, such that the signal developed on the bitline determines the degree of turn-on of the pFET device. An nFET device has its gate coupled to the sense node to detect and amplify the signal level thereof, and has its drain coupled to the data line. When sensing a low data signal, the signal developed on the bitline causes subthreshold voltage leakage current through the pFET device to charge the gate of the nFET device which is floating to amplify the signal developed on the bitline to pull down the precharged data line. When sensing a high data signal, the pFET device and the nFET device remain inactivated, and the data line remains at its precharge high voltage.

6552944, Apr 22, 2003

May 31, 2001

09/870755

John A. Fifield - Underhill VT
Toshiaki Kirihata - Poughkeepsie NY
Wing K. Luk - Chappqua NY
Jeremy K. Stephens - New Windsor NY
Daniel W. Storaska - Wappingers Falls NY

International Business Machines Corporation - Armonk NY

G11C 702

365208, 365203

A single bitline direct sensing architecture employs a 4 transistor sense amplifier circuit located in each memory array, wherein the transistors function to selectively transfer data bits from either a true bitline or a complement bitline of the bitline pair to a data line. The data line is preferably arranged over a plurality of memory arrays. The data line may or may not be shared for the read and write operations. One current source is additionally used to precharge the datalines in a read mode, performing the function of a digital sensing scheme by detecting a resistance ratio between the current source and the transistor driven by the bitline for the corresponding array. A simple inverter may be used for detecting a level of the data line determined by the resistance ratio. The bitline pair is sensed in a single ended fashion, eliminating the need for a cross-coupled pair of CMOS devices, and thus reducing the required layout area. By accessing the bitline pair individually, two sets of control signals for the pre-charge, EQ EQ are developed to allow for bitline shielding in the array.

6614714, Sep 2, 2003

Jan 22, 2002

10/055149

Louis L. Hsu - Fish Kill NY
Jeremy K. Stephens - New Windsor NY
Daniel W. Storaska - Walden NY
Li-Kong Wang - Montvale NJ

IBM Corporation - Armonk NY

G11C 818

365233, 36523003, 365191, 365194, 36518905

A data clock system for a semiconductor memory system is provided for performing reliable high-speed data transfers. The semiconductor memory system includes a plurality of data banks configured for storing data, the plurality of data banks in operative communication with a plurality of first data paths, each first data path in operative communication with a second data path. The data clock system includes a first clock path receiving a clock signal during a data transfer operation for transferring data between one data bank of the plurality of data banks and the second data path via one of the plurality of first data paths; and a second clock path receiving the clock signal from the first clock path and propagating the clock signal along therethrough, the second clock path including at least one clock driver. The transfer of data between the one of the plurality of first data paths and the second data path occurs upon receipt of the clock signal by the at least one clock driver. A method for propagating a clock signal in a semiconductor memory system is also provided for performing reliable high-speed data transfers.

6711078, Mar 23, 2004

Jul 1, 2002

10/064306

Ciaran J. Brennan - Essex Junction VT
John A. Fifield - Underhill VT
Jeremy K. Stephens - New Windsor NY
Daniel W. Storaska - Walden NY

International Business Machines Corporation - Armonk NY

B11C 700

365205, 365 63, 365203, 365222

A writeback and refresh circuit for a direct sense architecture memory wherein a plurality of primary sense amps are connected to a global data line and also to bitlines, each of which is coupled to an array of memory storage cells which are selected for write and read operations by a plurality of wordlines. A single secondary sense amp receives analog level data from the primary sense amps over the global data line, and includes a restore/writeback circuit which digitizes the data and then returns the digitized data over the global data line to the primary sense amp and back into the memory. A 2-cycle read/writeback operation is used for each memory read cycle, a first cycle read operation, and a second cycle writeback operation. The 2-cycle destructive read architecture eliminates the need for a cache and complex caching algorithms.

6751152, Jun 15, 2004

Oct 31, 2001

09/999379

Louis L. Hsu - Fishkill NY
Toshiaki K. Kirihata - Poughkeepsie NY
Daniel W. Storaska - Walden NY

International Business Machines Corporation - Armonk NY

G11C 800

36523006, 365203

A memory array architecture employs a full Vdd bitline precharged voltage and a low wordline boost voltage, which is less than Vdd plus the threshold voltage of the access transistor. In a write mode, a first low level of a data bit is almost fully written to a storage element, however a second high level of the data bit is not fully written to the storage element. In a read mode, the first low level of the data bit is fully read out from the storage element, however the second high level of the data bit is not read out by utilizing the access transistor threshold voltage. This allows a sensing signal only with the first voltage level transfer to the Vdd precharged BL. A reference WL is preferably used for generating a reference bitline voltage for a differential Vdd sensing scheme. Alternatively, a single BL digital sensing scheme may be used. Lowering the wordline voltage results in a reduction in power consumption by saving power on Vpp generator and support circuits, and a reduction in the size of the Vpp generator and support circuits, and also eliminates high Vpp voltage related problems such as dielectric breakdown and other reliability concerns while avoiding a complex decoding scheme and saving cost.

6775736, Aug 10, 2004

Jan 31, 2002

10/062812

Louis L. Hsu - Fish Kill NY
Rajiv J. Joshi - Yorktown Heights NY
Jeremy K. Stephens - New Windsor NY
Daniel W. Storaska - Walden NY

International Business Machines Corporation - Armonk NY

G06F 1200

711104, 711105, 36518904, 36523003

A self-timed data communication system for a wide data width semiconductor memory system having a plurality of data paths. The data communication system includes a plurality of data banks configured for storing data, wherein a corresponding data bank of the plurality of data banks is connected to a respective one data path of the plurality of data paths. The data communication system further includes circuitry for controlling the respective one data path in accordance with receipt of a monitor signal indicating that a data transfer operation has been initiated for transfer of data to or from the respective one data path. The circuitry for controlling includes circuitry for generating a control signal for controlling resetting of the respective one data path after data is transferred for preparation of a subsequent data transfer operation.