Darrell P Cox, 573471 S Raindrop Ct, Boise, ID 83706

7102769, Sep 5, 2006

Mar 15, 2001

09/809853

Darrell L. Cox - Boise ID, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 15/00

358 114, 358 115

A printer stores management or device configuration data specific to that printer in a memory unit to that printer. The printer then retrieves that data and transmits the data to a printer client device for storage. The printer client device uses the data with a printer driver running on the printer client device to provide appropriate messages (textual and graphic) to indicate an error occurring at the printer or the printer's configuration. A paper handling device connected to the printer may also provide error management and device configuration data to both the printer and the printer client device. In this way, the printer driver need not be prepared, at installation, with all the available error management and device data for all possible combinations of printer and paper handling devices.

5901325, May 4, 1999

May 20, 1996

8/650724

Darrell L. Cox - Boise ID

Hewlett-Packard Company - Palo Alto CA

G06F 1300

395821

The present invention, Extended Port Addressing (EPA), is a physical link layer communication protocol for enumeration of more than one device attached to the same parallel port on a desktop personal computer. EPA automatically determines individual devices as they are added or removed from the parallel port. EPA also allows time sharing of device drivers to a particular device without any one device driver locking the logical port. EPA extends plug `n` play characteristics by determining if other devices share the same parallel port when attached to a T-box EPA device.

5070529, Dec 3, 1991

Apr 17, 1989

7/339435

Richard Beaufort - Boise ID
James Sangroniz - Boise ID
Darrell Cox - Boise ID

Hewlett-Packard Company - Palo Alto CA

H05K 714

361415

An electrical circuit board interconnection system having motherboard 13 and a plurality of option board assemblies 10. Each option board assembly 10 has circuit board 15 to which is attached male pin connector assembly 12 on one surface and a mating female connector assembly 11 on the other surface. Both connector assemblies are oriented with pins 17 and female receptacles 18 parallel to the surface of the boards 15. Ejector levers 14 attached to female connector 11 to bear against male pin housing 36 to assist in disconnection option boards 10 from each other and motherboard 13. Power transfer bus 42 and signal transfer bus 43 interconnect the male and female pin connection 12 and 11 of each circuit board 15 to facilitate the sequential interconnection of a plurality of option board assemblies 10 to motherboard 13.

5969371, Oct 19, 1999

Jun 20, 1997

8/879999

Eric L. Andersen - Meridian ID
Darrell L. Cox - Boise ID

Hewlett-Packard Company - Palo Alto CA

G01N 2186

25055915

A system and method for sensing a leading edge of a document in an imaging scanner includes detecting a shadow adjacent the leading edge, the shadow being cast as a result of the edge being exposed to a light source. Light is reflected off of a white drive roller support surface for the document and is sensed by a photo sensor array. As the document is processed through the scanner, the leading edge is exposed to the light such that the leading edge casts a shadow onto the drive roller. The shadow is sensed by the photo sensor array which sends a signal to a microprocessor for computing whether a threshold amount of shadow has been detected for initiating image scanning of the document. Prior to the medium being exposed to the light, a contrast sensitivity level of the photo sensor array is increased, relative to a normal level, for detecting the shadow. Upon detecting the threshold amount of shadow, the contrast sensitivity level is returned to its normal level for continuing with normal image processing of the document.

5357621, Oct 18, 1994

Oct 12, 1993

8/135361

Darrell L. Cox - Boise ID

Hewlett-Packard Company - Palo Alto CA

G06F 1206
G06F 1300

395400

An expandable memory system including a central memory controller and one or more plug-in memory modules, each memory module having an on-board memory module controller coupled in a serial network architecture which forms a memory command link Each memory module controller is serially linked to the central memory controller. The memory system is automatically configured by the central controller, each memory module in the system is assigned a base address, in turn, to define a contiguous memory space without user intervention or the requirement to physically reset switches. The memory system includes the capability to disable and bypass bad memory modules and reassign memory addresses without leaving useable memory unallocated.