Darren L Abramson, 561301 Fogerty Ct, Folsom, CA 95630

6374321, Apr 16, 2002

Oct 27, 1999

09/428682

Stephen S. Pawlowski - Beaverton OR
Darren L. Abramson - Folsom CA
David I. Poisner - Folsom CA
Kishore K. Mishra - Folsom CA

Intel Corporation - Santa Clara CA

G06F 946

710260, 710263, 710266, 710 48, 710129

In some embodiments, the invention includes an apparatus including a host bridge coupled to a processor bus. The apparatus also includes an I/O bridge coupled to the host bridge, the I/O bridge including ports to receive an interrupt request signal in the form of address signals and data signals. Decode logic receives at least some of the address signals and data signals and to provide a decoded signal responsive thereto. A redirection table includes a send pending bit that is set responsive to the decoded signal.

6385671, May 7, 2002

Mar 29, 1999

09/280781

Mikal C. Hunsaker - El Dorado Hills CA
Darren L. Abramson - Folsom CA

Intel Corporation - Santa Clara CA

G06F 1300

710 28, 710 22, 710 33, 710 35, 710 52, 710 55, 709212, 709236, 370300, 370392, 370412, 370428, 370429, 370471, 370473, 370474, 714819, 714821, 712225

The present invention discloses a method and apparatus for processing a packet of data received from a direct memory access (DMA) engine. In one embodiment, a counter generates a self-ID code and increments the self-ID code after a bus reset. A formatter is coupled to the counter to format a start-of-packet (SOP) message which contains a self-ID field. The SOP message corresponds to the packet and the self-ID field corresponds to the self-ID code. A first-in-first-out (FIFO) is coupled to the formatter to store the SOP message and the packet. A comparator is coupled to the FIFO to compare the self-ID field of the message read from the FIFO with the self-ID code. A control circuit, which is coupled to the FIFO, flushes the packet if the self-ID field of the message is different than the self-ID code.

6473843, Oct 29, 2002

Feb 2, 2001

09/776221

Darren Abramson - Folsom CA
Joseph Bennett - Rancho Cordova CA

Intel Corporation - Santa Clara CA

G06F 1200

711162, 711161, 714 24, 713 2, 713300

The present invention relates to a method and apparatus for restoring a status data in a computer system. The circuit comprises: a read-only register for storing a read-only status value during a normal mode of operation; a first data path for supplying the read-only status value; a first control signal path for supplying a first control signal for controlling writing the supplied read-only status value into the read-only register during the normal mode of operation, the stored read-only status value being saved into a save area prior to removing power from the read-only register; a second data path for subsequently resupplying from the save area the previously stored read-only status value; a second control signal path for supplying a second control signal for controlling restoration of the re-supplied read-only status value into the read-only register during a restore mode of operation; and circuitry coupling the first and second data and control signal paths to the read-only register to facilitate the writing during the normal mode of operation and the restoration during the restore mode of operation.

6499077, Dec 24, 2002

Dec 30, 1999

09/475964

Darren L. Abramson - Folsom CA
Mikal C. Hunsaker - El Dorado Hills CA

Intel Corporation - Santa Clara CA

G06F 1300

710129, 710 5, 710 7, 710 20, 710 22, 710 33, 710 39, 710 52, 710104, 710107, 710112, 710126

A request interface device and method for operating the device and its components are described. The request interface device comprises a bus interface unit (BIU) and a requesting device. The requesting device generates a transfer request for data or command information, along with state information determining the manner in which the requester will transfer the data or command information associated with the request once the transfer request is granted. The transfer request and the associated state information are sent to the BIU, freeing the requester to generate new requests wile the first transfer request is waiting to be granted. The transfer request and associated information is stored in a queue within the BIU while the BIU logic gains access to the host bus. Once the transfer request is granted, it is sent over the host bus to its target while the associated state information is concurrently reflected back to the requestor to be used by the requester to complete the data or command information transfer.

6502146, Dec 31, 2002

Mar 29, 2000

09/537087

Norman J. Rasmussen - Hillsboro OR
Brad W. Hosler - Portland OR
Darren Abramson - Folsom CA
Michael J. McTague - Portland OR

Intel Corporation - Santa Clara CA

G06F 1300

710100, 710 63, 710313

Apparatus and methods to control an external bus. In one embodiment, an apparatus includes an external bus port and an external bus controller. The external bus controller can include a first register interface to receive a first set of data and a second register interface to receive a second set of data. The external bus controller can send the first set of data and the second set of data to said external bus port.

6529980, Mar 4, 2003

Jan 15, 1997

08/784199

Darren L. Abramson - Folsom CA

Intel Corporation - Santa Clara CA

G06F 100

710108, 710110, 710309

A protocol for superimposing status information onto an arbitration scheme between a first bus agent and a second bus agent. One embodiment of the arbitration scheme uses a grant signal and a request signal to arbitrate for use of a bus. The second bus agent may request to use the bus by asserting a request signal, which is received by a bus arbitration circuit. The bus arbitration circuit may or may not reside within the first bus agent. The bus arbitration logic acknowledges the request by asserting a grant signal, which is received by the second bus agent. A specific relationship between an address phase and the arbitration signals allows the first bus agent to pass status information to the second bus agent via the grant signal. The specific relationship between an address phase and the arbitration signals is a condition that typically does not occur where the arbitration signals are used to arbitrate for use of the bus.

6594717, Jul 15, 2003

Sep 9, 2002

10/237113

Norman J. Rasmussen - Hillsboro OR
Brad W. Hosler - Portland OR
Darren Abramson - Folsom CA
Michael J. McTague - Portland OR

Intel Corporation - Santa Clara CA

G06F 1300

710100, 710 63, 710313

Apparatus and methods to control an external bus. In one embodiment, an apparatus includes an external bus port and an external bus controller. The external bus controller can include a first register interface to receive a first set of data and a second register interface to receive a second set of data. The external bus controller can send the first set of data and the second set of data to said external bus port.

6643716, Nov 4, 2003

Mar 29, 1999

09/280908

Mikal C. Hunsaker - El Dorado Hills CA
Darren L. Abramson - Folsom CA
Rajesh Raman - Chandler AZ
Bret T. Connell - Sacramento CA

Intel Corporation - Santa Clara CA

G06F 1300

710 21, 710 20, 710 22, 710 29, 710 30, 710 33, 710 35, 710 52, 709206, 709207, 709212, 709230, 709231, 709236, 370235, 370300, 370349, 370389, 370466, 370467, 370470, 370471, 370473, 370474, 370476

The present invention discloses a method and apparatus for processing a packet of data received by a first-in-first-out (FIFO). In one embodiment, a message in the packet of data is recognized. Based on a plurality of control bits encoded in the message, a delimiting condition in the packet of data is determined. An operation is performed which is responsive to the delimiting condition. The operation controls the transfer of the packet of data from the FIFO to a memory.