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Daryl H Lieu, 48254 Ficus Ter, Sunnyvale, CA 94086

Known as:
Darryl H Lieu

Daryl Lieu Phones & Addresses

254 Ficus Ter, Sunnyvale, CA 94086    408-7491032   

150 Pasito Ter, Sunnyvale, CA 94086    408-8300143   

Menlo Park, CA   

Stanford, CA   

Pittsburgh, PA   

San Jose, CA   

San Mateo, CA   

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Daryl Lieu resumes & CV records

Resumes

Daryl Lieu Photo 7

Senior Member Of Technical Staff

Location:
Sunnyvale, CA
Industry:
Computer Hardware
Work:
Amd
Senior Member of Technical Staff Sun Microsystems Jan 2002 - Jun 2004
Rtl Design Engineer
Education:
Stanford University Jan 2001 - Mar 2002
Master of Science, Masters, Electrical Engineering Carnegie Mellon University 1997 - 2000
Bachelors, Bachelor of Science, Economics, Computer Engineering
Skills:
Microprocessors, Physical Design, Logic Design, Circuit Design, Microarchitecture, Asic, Computer Architecture, Eda, Verilog, Semiconductors, Low Power Design, High Performance Computing, Hardware, Vlsi
Daryl Lieu Photo 8

Daryl Lieu

Publications & IP owners

Us Patents

Superscalar Register-Renaming For A Stack-Addressed Architecture

US Patent:
8539397, Sep 17, 2013
Filed:
Jun 11, 2009
Appl. No.:
12/482977
Inventors:
Ranganathan Sudhakar - Santa Clara CA, US
Daryl Lieu - Sunnyvale CA, US
Debjit Das Sarma - San Jose CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 17/50
US Classification:
716100, 716101
Abstract:
A system and method for increasing processor throughput by decreasing a loop critical path. In one embodiment, a table comprises multiple stack entries, each comprising an x87 floating-point (FP) stack specifier. The combinatorial logic for operand translation of N FP instructions per clock cycle may require N instantiated copies of a combinatorial logic block. Each instantiated copy may determine a new ordering of the stack entries. Control logic may receive necessary information from the corresponding N FP instructions and determine a corresponding combined computational effect, or stack reordering, on entries within the table based on two or more instructions. Resulting control signals are conveyed to the N instantiated copies. A resulting accumulative delay from an input of the first copy to the output of the Nth copy may be less than or equal to (N−1)*time_delay versus a longer N*time_delay.

Method For Floating Point Round To Integer Operation

US Patent:
2011005, Mar 3, 2011
Filed:
Aug 28, 2009
Appl. No.:
12/549724
Inventors:
Kevin Hurd - Ft. Collins CO, US
Daryl Lieu - Menlo Park CA, US
Kelvin Goveas - Austin TX, US
Scott Hilker - Campbell CA, US
International Classification:
G06F 7/483
US Classification:
708497
Abstract:
An apparatus and method for computing a rounded floating point number. A floating point unit (FPU) receives an instruction to round a floating point number to a nearest integral value and retrieves a binary source operand having an exponent of a fixed first number of bits and a mantissa of a fixed second number of bits. If the unbiased exponent value is greater than or equal to zero and less than the fixed second number, the FPU generates a mask having N consecutive ‘1’ bits beginning with the least significant bit and whose remaining bits have a value of ‘0’, where N is equal to the fixed second number minus the unbiased exponent value. The FPU computes a bitwise OR of the source operand with the mask, increments the result if the instruction is to round up, and computes a bitwise AND of the result with the inverse of the mask.

Possible Relatives

Cynthia Lieu  Deborah M Lieu  Danny A Lieu  Dao T Lieu  Don Lieu  George Y Lieu  Hao C Lieu  Daryl Y Johnson  Daryl L White  Daryl G Jolly 

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