David W Chrudimsky, 597320 Via Correto Dr, Austin, TX 78749

6745357, Jun 1, 2004

Jul 9, 2001

09/901411

David W. Chrudimsky - Austin TX
Stephen C. Horne - Austin TX
James S. Blomgren - Austin TX
Michael R. Seningen - Austin TX

Intrinsity, Inc. - Austin TX

G01R 3128

714726, 714731

A method and apparatus for random-access scan of a network of dynamic logic or N-NARY logic that includes sequentially clocked precharge logic gates and one or more scan gates ( ) driven by multiple overlapping clock signals generated from a clock generation circuit ( ) coupled to a clock spine ( ). Each clocked precharge logic gate and each scan gate include a logic tree ( ) with one or more evaluate nodes, a precharge circuit ( ), an evaluate circuit ( ), and one or more output buffers ( ). Each scan gate further includes a scan circuit ( ) that accepts scan control signals ( , and ) and couples to one or more scan registers ( ) in a RAM-like architecture. Scan control signals operate to capture the state of the output buffers of the scan gate, and to force the output buffers of the scan gate to a preselected level.

7428172, Sep 23, 2008

Jul 17, 2006

11/487863

Jon S. Choy - Austin TX, US
David W. Chrudimsky - Austin TX, US
Thomas Jew - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G11C 11/34

36518522, 365 24

A program voltage is applied to the drain electrode of a floating gate transistor to program the floating gate transistor. Concurrent with the application of the program voltage, a current based on the voltage at the source electrode of the floating gate transistor is compared with a threshold current to verify the programming of the floating gate transistor. When the bit cell current falls below the threshold current, the floating gate transistor is considered to be sufficiently programmed and the next floating gate transistor to be programmed is selected. Further, the program voltage supply emulates the selection circuitry used to select between the bit cells so as to model the voltage drop caused by the selection circuitry between the program voltage supply and the drain electrode of the floating gate transistor being programmed. The program voltage supply adjusts the output program voltage based on the modeled voltage drop.

7446566, Nov 4, 2008

Oct 16, 2007

11/873099

David Chrudimsky - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H03K 19/094
H03K 19/0175
H03L 5/00

326 68, 327333

A level shifter circuit includes first and second cross-coupled P channel transistors, first and second cross-coupled N channel transistors, and first and second inverters. The first and second P channel transistors are coupled to receive a first power supply voltage. The first and second cross-coupled N channel transistors are coupled to the first and second P channel transistors. The first and second inverters are coupled to the first and second N channel transistors and are coupled to receive a second power supply voltage that is lower than the first power supply voltage. The first and second N channel transistors have a lower, substantially zero volts, threshold voltage and can be controlled by a low voltage signal while limiting a leakage current.

7542351, Jun 2, 2009

May 31, 2007

11/756192

Jon S. Choy - Austin TX, US
David W. Chrudimsky - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G11C 16/06

36518525, 36518519, 36518514, 36518523, 36518526, 36518529, 36518531

An integrated circuit () comprises a plurality of non-volatile memory cells () and a charge distribution ramp rate control circuit (). Each memory cell of the array () includes a charge storage region and a plurality of terminals. The charge distribution ramp rate control circuit includes a capacitor () having a first plate electrode coupled to at least one terminal of the plurality of terminals, and a second plate electrode. The charge distribution ramp rate control circuit further includes a bandgap generated current source () for providing a reference current to determine a ramp rate of a voltage at the at least one terminal.

7564716, Jul 21, 2009

Nov 16, 2006

11/560554

Ronald J. Syzdek - Austin TX, US
David W. Chrudimsky - Austin TX, US
Xiaojie He - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G11C 11/34

3651852, 36521001, 36521014

A read reference level of a plurality of read reference is determined for a set of bit cells of a non-volatile memory array. An indicator of the read reference level is stored in a non-volatile storage location associated with the set of bit cells. The indicator of the read reference level is accessed in response to a read access operation to the set of bit cells and a value stored at a memory location of the set of bit cells is sensed based on the indicator of the read reference level, whereby the memory location of the set of bit cells is associated with the read access operation.

7692989, Apr 6, 2010

Apr 26, 2007

11/740331

Padmaraj Sanjeevarao - Austin TX, US
David W. Chrudimsky - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G11C 7/00

365205, 365191, 365201, 36518914, 36518915

A memory has first and second memory arrays and first and second sense amplifiers coupled to the first and second memory arrays, respectively. A verify data line is coupled to first outputs of the first sense amplifier and the second sense amplifier as well as to a program/erase controller. The verify data line has a first logic circuit having a first input coupled to the first output of the first sense amplifier and an output. A second logic circuit has a first input coupled to the output of the first logic circuit, a second input coupled to the first output of the second sense amplifier, and an output. A global data line is coupled to a second output of the first sense amplifier and a second output of the second sense amplifier. A global sense amplifier is coupled to the global data line.

7701785, Apr 20, 2010

Jun 23, 2008

12/144332

Padmaraj Sanjeevarao - Austin TX, US
Tahmina Akhter - Austin TX, US
David W. Chrudimsky - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G11C 7/00

36518909, 365226

A memory including a data line, a sense amplifier, and an array of memory cells. The memory includes a transistor for coupling the data line to memory cells of the array for reading. The transistor is biased at a voltage that is higher than a voltage that the data line is biased during precharging. The transistor is part of a regulation circuit. The regulation circuit includes transistors with a higher dielectric breakdown voltage than transistors of the sense amplifier.

7733126, Jun 8, 2010

Mar 31, 2009

12/415159

Jon Choy - Austin TX, US
David W. Chrudimsky - Austin TX, US
Padmaraj Sanjeevarao - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H03K 19/0175

326 68, 326 81

A first logic state is at a first output voltage level at a first output of a level shifter that selects a first negative regulation voltage level in response to the first logic state. A negative supply voltage begins at first potential and decreases to the first negative regulation voltage level. The first output voltage level decreases as the negative supply voltage decreases. The first output of the level shifter is switched from the first logic state to a second logic state in response to the negative supply voltage reaching the first negative regulation voltage level. The second logic state is provided at a second output voltage level that selects a second negative regulation voltage level for the negative regulation voltage. The first output of the level shifter remains at the second logic state but is reduced in voltage.