David H Kamp, 7019655 Clubhouse Dr, Parker, CO 80138

6658608, Dec 2, 2003

Sep 21, 1999

09/400210

David A. Kamp - Monument CO, 80132-7920
Gary F. Derbenwick - Colorado Springs CO, 80918

G11C 2900

714718, 365145, 257295

A ferroelectric integrated circuit memory device includes: a plurality of memory cells, each including a ferroelectric material, a plurality of conducting lines, each connected to or connectable to a selected one of the memory cells; a drive circuit for applying a predetermined voltage for a predetermined time to a selected one of the conducting lines, the predetermined voltage and time being the normal voltage and time required to perform write or read functions to the memory cell, a function selected from the group of: writing a logic state to the selected memory cell, and reading the selected memory cell; and a mode control circuit responsive to an external signal for adjusting the predetermined voltage or the predetermined time to perform an operation selected from the group consisting of: a partial read of the selected memory cell, and a partial write of the selected memory cell; and applying ferroelectric stress to the memory cell. A known logic state is written to the memory cells, the cells are heated, and then read to provide output data indicative of the likelihood of premature failure for each of the memory cells. Ferroelectric stress is applied to the cells either before or after the cells are written to by repeatedly applying a voltage to the cells corresponding to a logic state opposite that of the written logic state.

6760246, Jul 6, 2004

May 1, 2002

10/136210

David A. Kamp - Monument CO
Alan D. DeVilbiss - Colorado Springs CO

Celis Semiconductor Corporation - Colorado Springs CO

G11C 1122

365145, 365 65

A ferroelectric field effect transistor (FET) has a gate, source, drain, and substrate. A negative voltage is applied to the gate. Ground potential is applied to the source, drain, and substrate. The negative voltage has a magnitude at least equal to the coercive voltage of the FET. A positive voltage is then applied to the gate. Ground potential is applied to the source and substrate. The positive voltage is no less than the coercive voltage. Either a positive voltage or a ground potential is applied to the drain to write a logic state to the FET. A voltage is applied to the gate. Ground potential is applied to the source. A positive voltage is applied to the drain. The drain current is measured and compared to a compare current. The relative size of the drain current compared to the compare current is indicative of the stored logic state in the FET.

8411505, Apr 2, 2013

Nov 12, 2010

12/945203

David A. Kamp - Monument CO, US

EM Microelectronic-Marin SA - Marin

G11C 11/34

36518504, 365211, 365196, 36518916

The self-powered detection device comprises a Non-Volatile Memory (NVM) unit () formed at least by a NVM cell and a sensor which is activated by a physical or chemical action or phenomenon, this sensor forming an energy harvester that transforms energy from said physical or chemical action or phenomenon into an electrical stimulus pulse, said NVM unit being arranged for storing in said NVM cell, by using the electrical power of said electrical stimulus pulse, a bit of information relative to the detection by said sensor, during a detection mode of the self-powered detection device, of at least one physical or chemical action or phenomenon applied to it with at least a given strength or intensity and resulting in a voltage stimulus signal provided between a set control terminal (SET) and a base terminal (SET *) of said NVM unit with at least a given set voltage. The self-powered detection device comprises a read circuit () or is arranged to be coupled to such a read circuit and further comprises a clamp circuit () located between the sensor and the NVM unit, this clamp circuit being arranged for passing said voltage stimulus signal on a set line connecting the sensor and the set control terminal of the NVM unit, this voltage stimulus pulse having a polarity corresponding to a set polarity of said NVM cell, and for blocking other voltage signals having approximately an amplitude corresponding to said set voltage or higher and an inverse polarity relative to the set polarity of said NVM cell, in order to avoid a possible erase of this NVM cell by such other voltage signals.

8422293, Apr 16, 2013

Nov 12, 2010

12/945138

David A. Kamp - Monument CO, US
Filippo Marinelli - Lussy-sur-Morges, CH
Thierry Roz - Payerne, CH

EM Microelectronic-Marin SA - Marin

G11C 16/22

36518504, 36518521, 36518523, 365227, 365228

The self-powered detection device comprises a non-volatile memory cell and a sensor activated by a physical or chemical action or phenomenon, this sensor forming an energy harvester transforming energy from the physical or chemical action orphenomenon into an electrical stimulus pulse, the memory cell arranged for storing, by using electrical power of the electrical stimulus pulse, at least a bit of information relative to detection by the sensor of at least a first physical or chemical action or phenomenon. The non-volatile memory cell comprises a FET transistor having a control gate, a first diffusion defining a first input and a second diffusion defining a second input. This FET transistor is set to its written logical state from its initial logical state when, in a detection mode, it receives on a set terminal a voltage stimulus signal resulting from the first physical or chemical action or phenomenon.

8422317, Apr 16, 2013

Nov 12, 2010

12/945168

David A. Kamp - Monument CO, US
Filippo Marinelli - Lussy-sur-Morges, CH
Thierry Roz - Payerne, CH

EM Microelectronic-Marin SA - Marin

G11C 7/22
G11C 5/14

36518916, 365226

The self-powered detection device comprises a Non-Volatile Memory (NVM) unit formed by at least a NVM cell and a sensor activated by a physical or chemical action or phenomenon, the NVM unit arranged for storing in the NVM cell, by using electrical power of the electrical stimulus pulse, a bit of information relative to detection by the sensor, during a detection mode of the self-powered detection device, of at least one physical or chemical action or phenomenon applied to it with at least a given strength or intensity and resulting in a voltage stimulus signal provided between a set control terminal and a base terminal of the NVM unit with at least a given set voltage.

8604865, Dec 10, 2013

May 23, 2012

13/478485

Nicolas Pillin - St-Sulpice, CH
David A. Kamp - Monument CO, US

EM Microelectronic-Marin S.A. - Marin

H03K 17/687

327427, 327434

A RFID transponder includes an electronic circuit and an antenna, the electronic circuit being integrated in a p-type substrate and comprising a modulator formed by a PMOS transistor whose drain, electrically connected to a pad of the antenna, and source, connected to the ground of the electronic circuit, are arranged in an n-type well provided in the p-type substrate. The PMOS transistor has a gate driven by a driving circuit which is arranged for providing at least a negative voltage, this negative voltage being low enough for turning on this PMOS transistor in response to a control signal provided by a logical unit of the electronic circuit.

2008023, Sep 25, 2008

Mar 23, 2007

11/690607

David A. Kamp - Monument CO, US

G06F 17/50

716 4, 716 11

A semiconductor layout design analyzer alerts a user of areas in a semiconductor layout design that may be candidates for radiation induced inversion. The analyzer includes means for gathering information, means for identifying, and means for alerting the user. The means for gathering gathers, from the layout design, placement information for thick oxide, low-doped p-type single crystal silicon, and n-type silicon. The means for identifying identifies, in the layout design, thick oxide overlaying low-doped p-type single crystal silicon and abutting n-type silicon. The means for alerting the user alerts the user of the identified areas of thick oxide.

2011011, May 12, 2011

Nov 17, 2009

12/620365

David A. KAMP - Monument CO, US
Filippo MARINELLI - Lussy-sur-Morges, CH
Thierry ROZ - Payerne, CH

EM MICROELECTRONIC-MARIN SA - Marin

G11C 7/20

36518916

The external event detection device comprises an electronic unit () and an external event sensor (), the electronic unit having at least a non-volatile memory cell (, T) in which data relative to at least one external event detected by the external event sensor can be stored. According to the invention, the external event sensor defines an energy harvester that transforms energy from said at least one external event into electrical energy contained in an electrical stimulus pulse provided to the electronic unit. The electronic unit is arranged for storing said data by using only the electrical energy contained in the electrical stimulus pulse. In particular, the non-volatile memory cell is directly set to its written logical state from its initial logical state by the electrical stimulus pulse provided by said energy harvester. In a preferred embodiment, the electronic unit further comprises a set circuit () comprising a second FET transistor (T) arranged between the ground of the electronic unit and the drain of a first FET transistor (T) defining the non-volatile memory cell, this switch having a control gate connected to the control gate of the first FET transistor. The second FET transistor is turned on when an electrical stimulus pulse is provided to the electronic unit, connecting the drain (DRN) of the first FET transistor (T) to ground and thus allowing the secure setting of the non-volatile memory cell.