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David H Kung, 46New York, NY

David Kung Phones & Addresses

New York, NY   

Hanover, NH   

Mount Vernon, NY   

New Haven, CT   

Boston, MA   

Syracuse, NY   

Bronxville, NY   

415 Main St APT 11B, New York, NY 10044   

Work

Company: ADVANCED ICU CARE Address: 999 Executive Parkway Dr Suite 320, Saint Louis, MO 63141 Phones: 314-5146000 (Phone)

Education

School / High School: Tufts University 2006

Languages

English

Ranks

Certificate: American Board of Internal Medicine Certification in Internal Medicine

Mentions for David H Kung

Career records & work history

Medicine Doctors

David Kung Photo 1

Dr. David H Kung, Saint Louis MO - MD (Doctor of Medicine)

Specialties:
Critical Care Medicine
Pulmonary Critical Care Medicine
Address:
999 Executive Parkway Dr Suite 210, Saint Louis, MO 63141
314-5146005 (Phone) 866-4971239 (Fax)
ADVANCED ICU CARE
999 Executive Parkway Dr Suite 320, Saint Louis, MO 63141
314-5146000 (Phone)
525 E 68Th St Suite 96, New York, NY 10065
20 York St Suite T-209, New Haven, CT 06510
203-6882259 (Phone) 203-6885599 (Fax)
Languages:
English
Education:
Medical School
Tufts University
Graduated: 2006

David Y. Kung

Specialties:
Surgery , Neurological
Work:
Arnot Medical ServicesDavid C Y Kung MD
300 Madison Ave, Elmira, NY 14901
607-7342574 (phone) 607-7343303 (fax)
Site
Education:
Medical School
Natl Defense Med Ctr, Taipei, Taiwan (385 03 Pr 1/71)
Graduated: 1967
Procedures:
Carpal Tunnel Decompression, Craniotomy, Lumbar Puncture, Spinal Fusion, Spinal Surgery, Spinal Cord Surgery
Conditions:
Intervertebral Disc Degeneration
Languages:
Chinese, English
Description:
Dr. Kung graduated from the Natl Defense Med Ctr, Taipei, Taiwan (385 03 Pr 1/71) in 1967. He works in Elmira, NY and specializes in Surgery , Neurological. Dr. Kung is affiliated with Arnot Ogden Medical Center.

David S. Kung

Specialties:
Plastic Surgery, Oral & Maxillofacial Surgery
Work:
Kung Plastic Surgery PA
5454 Wisconsin Ave STE 635, Chevy Chase, MD 20815
301-9868878 (phone) 301-9868879 (fax)
Education:
Medical School
Harvard Medical School
Graduated: 1992
Procedures:
Breast Reconstruction, Periodontics, Rhinoplasty
Conditions:
Cleft Palate and Cleft Lip, Tempromandibular Joint Disorders (TMJ)
Languages:
Chinese, English
Description:
Dr. Kung graduated from the Harvard Medical School in 1992. He works in Chevy Chase, MD and specializes in Plastic Surgery and Oral & Maxillofacial Surgery. Dr. Kung is affiliated with Childrens National Health System, Sibley Memorial Hospital and Suburban Hospital.
David Kung Photo 2

David Hans Kung

Specialties:
Internal Medicine
Education:
Tufts University (2006)
David Kung Photo 3

David Kakin Kung

Specialties:
Neurological Surgery
Education:
Yeshiva University (2006)
David Kung Photo 4

David Kung, New Haven CT

Specialties:
Internist
Address:
20 York St, New Haven, CT 06510
Education:
Tufts University, School of Medicine - Doctor of Medicine
Yale New Haven Psychiatric Hospital - Residency - Internal Medicine
Yale New Haven Psychiatric Hospital - Internship - Internal Medicine
Board certifications:
American Board of Internal Medicine Certification in Internal Medicine
American Board of Internal Medicine Sub-certificate in Pulmonary Disease (Internal Medicine)

License Records

David Hans Kung

Address:
New York, NY 10044
Licenses:
License #: MD449732 - Active
Category: Medicine
Type: Medical Physician and Surgeon

David H Kung

Address:
415 Main St APT 11B, New York, NY
Phone:
314-5146005
Licenses:
License #: 117494 - Active
Category: Health Care
Issued Date: Sep 6, 2013
Effective Date: Sep 6, 2013
Expiration Date: Jan 31, 2018
Type: Medical Doctor

David Kung resumes & CV records

Resumes

David Kung Photo 36

Director At Barclays Capital

Position:
Director at Barclays Capital
Location:
Greater New York City Area
Industry:
Financial Services
Work:
Barclays Capital
Director
Credit Suisse First Boston Mar 2001 - Apr 2004
Vice President
Education:
Columbia University - Columbia Business School 2003 - 2004
EMBA
David Kung Photo 37

David Kung

Location:
Greater New York City Area
Industry:
Computer Hardware
David Kung Photo 38

Information Technology And Services Professional

Location:
Greater New York City Area
Industry:
Information Technology and Services
David Kung Photo 39

David Kung

Location:
Greater New York City Area
Industry:
Real Estate
David Kung Photo 40

David Kung

Location:
United States

Publications & IP owners

Us Patents

Timing-Driven Global Placement Based On Geometry-Aware Timing Budgets

US Patent:
6480991, Nov 12, 2002
Filed:
Apr 11, 2001
Appl. No.:
09/832623
Inventors:
David S. Kung - Chappaqua NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1750
US Classification:
716 8, 716 10
Abstract:
A system and method for timing-closed placement which also takes wirelength and congestion into consideration. In one aspect, the system and method of timing driven placement according to the present invention incorporates a timing budget management technique which satisfies triangle parity and inequality, a timing-driven quadrisection placement strategy based on flexible timing window configurations to minimize the wirelength and congestion during each mincut quad-partition of top-down hierarchy, and a linear programming formulation incorporating bin capacity, channel capacity and congestion criticality.

System And Method For Fast Interconnect Delay Estimation Through Iterative Refinement

US Patent:
6601223, Jul 29, 2003
Filed:
Sep 29, 2000
Appl. No.:
09/675634
Inventors:
Ruchir Puri - New Rochelle NY
David S. Kung - Chappaqua NY
Anthony Drumm - Rochester MN
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1750
US Classification:
716 6, 716 1, 716 2, 716 4, 716 5
Abstract:
A system and method are proposed for estimating interconnect delay in an Integrated Circuit (IC). A formula for effective capacitance is derived which considers the effect of slew as well as resistive shielding of capacitance, thus yielding more accurate delays for both the interconnects and the source driver (transistor gate). In the system and method, a resistor-capacitor (RC) tree model is used for iterative calculations of effective capacitance and slew for each RC tree node. The effective capacitance is determined for each node by proceeding outward from the source to the sinks, and the slew for each node is determined, using the effective capacitances just determined, by proceeding inward from the sinks to the source node. Once the source node slew determined at a previous iteration is within a specified threshold of the source node slew in the present iteration, the method stops and stores the present iteration values as the final estimates.

Integrated Circuit Logic With Self Compensating Block Delays

US Patent:
7084476, Aug 1, 2006
Filed:
Feb 26, 2004
Appl. No.:
10/787488
Inventors:
Puneet Gupta - LaJolla CA, US
David S. Kung - Chappaqua NY, US
Daniel L. Ostapko - Mahopac NY, US
Assignee:
International Business Machines Corp. - Armonk NY
International Classification:
H01L 29/00
US Classification:
257499, 257501
Abstract:
An integrated circuit (IC) including at least one combinational logic path. The combinational logic path includes two types of logic blocks cells that compensate each other for fabrication parameter effects on cell transistors. The two types may be dense cells with field effect transistor (FET) gates on contacted pitch and isolated cells with FET gates on wider than contacted pitch. Dense cell delay changes from the FET gates being printed out of focus are offset by isolated cell delay changes.

Three Dimensional Integrated Circuit

US Patent:
7312487, Dec 25, 2007
Filed:
Aug 16, 2004
Appl. No.:
10/919121
Inventors:
Syed M. Alam - Cambridge MA, US
Ibrahim M. Elfadel - Ossining NY, US
Kathryn W. Guarini - Yorktown Heights NY, US
Meikei Ieong - Wappingers Falls NY, US
Prabhakar N. Kudva - New York NY, US
David S. Kung - Chappaqua NY, US
Mark A. Lavin - Katonah NY, US
Arifur Rahman - Freemont CA, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 29/80
US Classification:
257278, 257E27026, 257E21614, 438455
Abstract:
A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e. g. , silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

Three Dimensional Integrated Circuit And Method Of Design

US Patent:
7723207, May 25, 2010
Filed:
Apr 19, 2007
Appl. No.:
11/737598
Inventors:
Syed M. Alam - Cambridge MA, US
Ibrahim M. Elfadel - Ossining NY, US
Kathryn W Guarini - Yorktown Heights NY, US
Meikei Ieong - Wappingers Falls NY, US
Prabhakar N. Kudva - New York NY, US
David S. Kung - Chappaqua NY, US
Mark A. Lavin - Katonah NY, US
Arifur Rahman - Freemont CA, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/30
US Classification:
438455, 438183, 257419
Abstract:
A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e. g. , silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

Enabling Statistical Testing Using Deterministic Multi-Corner Timing Analysis

US Patent:
8560994, Oct 15, 2013
Filed:
Apr 24, 2012
Appl. No.:
13/454795
Inventors:
Bhavna Agrawal - Armonk NY, US
David S. Kung - Chappaqua NY, US
Jinjun Xiong - White Plains NY, US
Vladimir Zolotov - Putnam Valley NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716113, 716108, 716132, 716134, 716136
Abstract:
In one embodiment, the invention is a method and apparatus for variation enabling statistical testing using deterministic multi-corner timing analysis. One embodiment of a method for obtaining statistical timing data for an integrated circuit chip includes obtaining deterministic multi-corner timing data for the integrated circuit chip and constructing the statistical timing data from the deterministic multi-corner timing data.

Three Dimensional Integrated Circuit And Method Of Design

US Patent:
2008004, Feb 21, 2008
Filed:
Aug 30, 2007
Appl. No.:
11/847608
Inventors:
Syed Alam - Cambridge MA, US
Ibrahim Elfadel - Ossining NY, US
Kathryn Guarini - Yorktown Heights NY, US
Meikei Ieong - Wappingers Falls NY, US
Prabhakar Kudva - New York NY, US
David Kung - Chappaqua NY, US
Mark Lavin - Katonah NY, US
Arifur Rahman - Freemont CA, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPERATION - Armonk NY
International Classification:
H01L 29/04
US Classification:
257074000, 257E27026
Abstract:
A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

System And Method For Improving Logic Synthesis In Logic Circuits

US Patent:
6253356, Jun 26, 2001
Filed:
Mar 24, 1998
Appl. No.:
9/046831
Inventors:
David S. Kung - Chappaqua NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1750
US Classification:
716 5
Abstract:
A method of fanout optimization includes the steps of inputting a net list including fanout regions, each fanout region having sources, each source being coupled to at least one sink, determining a gain for inverters to be placed in a buffer tree, wherein the gain has a same value for all inverters to be placed within the tree, computing a number of inverters used to couple the source to each sink and introducing inverters into the buffer tree to couple the source to each sink. A system for employing the method of fanout optimization is also described.

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