David H Ma, 48208 Preatonwood Dr, Apex, NC 27539

6667919, Dec 23, 2003

Sep 26, 2002

10/256181

David Suitwai Ma - Cary NC
Paul Edward Brucke - Durham NC
Rainer Hoehler - Durham NC

Infineon Technologies, AG - Munich

G11C 700

365201, 365203

A circuit and method for testing a semiconductor memory device using a row compression test mode is provided. The testing circuit includes at least one equalizer circuit for supplying a first voltage level to one of at least one true bitline or at least one complement bitline during a test mode; an equalizing line for coupling a plurality of equalizer circuits along a wordline; and a comparator for comparing a second voltage on the equalizing line during the test mode to a reference voltage, wherein if the second voltage is less than the reference voltage, the wordline is defective.

6702589, Mar 9, 2004

Aug 16, 2002

10/222693

David SuitWai Ma - Cary NC
Bing Ren - Cary NC
James J. Dietz - Durham NC

Infineon Technologies AG - Munich

H01R 909

439 72, 439912

An apparatus for mounting a semiconductor device to a circuit board for testing is disclosed. The semiconductor device includes semiconductor circuitry and leads to connect the semiconductor circuitry to the circuit board. Additionally, the semiconductor device is decapped so that at least a portion of the semiconductor circuitry is exposed. The apparatus includes a frame and a fastener. The frame is adapted to mate with the semiconductor device, and forms an opening for accessing the semiconductor circuitry and an edge surface for receiving the semiconductor device. The fastener is connected with the frame for removably connecting the frame to the circuit board. By using a frame instead of a socket, the distance to the semiconductor device once the device is mounted to the circuit board, and particularly the top side of the semiconductor device, can be reduced so that the device may be tested using a probe.

6721180, Apr 13, 2004

Jul 31, 2002

10/209025

Guenter Gerstmeier - Chapel Hill NC
David SuitWai Ma - Cary NC
Tao Wang - Cary NC

Infineon Technologies AG - Munich

H05K 720

361695, 622592, 165 803, 165121, 361719, 361720, 454184

A cooling hood for a circuit board is provided. The circuit board includes at least one semiconductor device. The cooling hood includes a duct mounted onto the circuit board and surrounding at least a portion of the semiconductor device. The duct forms an inlet and an outlet. A cooling medium enters the duct through the inlet and exits the duct through the outlet.

6754113, Jun 22, 2004

Sep 24, 2002

10/253148

David Suitwai Ma - Cary NC
Paul Edward Brucke - Durham NC

Infineon Technologies AG - Munich

G11C 700

365200, 365201

A data topography correction circuit for a semiconductor memory device and method for testing the device is provided. The data topography correction circuit includes a redundant hit circuit for determining if a redundant element has been used to replace a defective element; and a redundant topology correction scrambler circuit for converting data from a data topology of the defective element to a data topology of the redundant element. The method includes the steps of providing an address of a memory array element of the device to be tested; determining if the memory array element has been replaced with a redundant element; and, if the memory array element has been replaced, correcting test data to the data topology of the redundant element.

6845048, Jan 18, 2005

Sep 25, 2002

10/255767

George W. Alexander - Durham NC, US
Jennifer F. Huckaby - Raleigh NC, US
Steven M. Baker - Apex NC, US
David S. Ma - Cary NC, US

Infineon Technologies AG - Munich

G11C 114074
G11C 114193
H03K 17693

36518902, 36518909, 365226, 327407, 327 99

A system and method for monitoring internal voltage sources in an integrated circuit, such as a DRAM integrated circuit, includes an internal analog multiplexing circuit, an internal analog-to-digital converter, and an interface circuit. Through the analog multiplexing circuit, the analog-to-digital converter sequentially connects to each voltage source and converts the measured voltage level of the source to a binary word. The interface circuit presents the binary word, e. g. , serially, to test equipment off the integrated circuit.

6903982, Jun 7, 2005

Oct 10, 2002

10/269005

David SuitWai Ma - Cary NC, US
Aiqin Chen - Cary NC, US

Infineon Technologies AG - Munich

G11C007/00

36518901, 36518903, 365203, 36523003

An integrated memory circuit and corresponding method for segmenting bit lines are provided, where the integrated memory circuit includes a sense amplifier, a layered bit line in signal communication with the sense amplifier, several segment pass transistors in signal communication with the layered bit line, several segmented bit lines, each in signal communication with a corresponding one of the several segment pass transistors, respectively, several memory cell pass transistors in signal communication with one of the several segmented bit lines, and a plurality of memory cell capacitors, each in signal communication with a corresponding one of the plurality of memory cell transistors, respectively; and where the corresponding method for segmenting bit lines includes receiving a memory cell address, activating a memory cell pass transistor with a wordline corresponding to the memory cell address, receiving a signal indicative of the memory cell charge level on a segmented bit line through the memory cell transistor, activating a segment pass transistor corresponding to the memory cell address, receiving a signal indicative of the memory cell charge level on a layered bit line through the segment pass transistor, and receiving a signal indicative of the memory cell charge level at the sense amplifier through the layered bit line.

7071724, Jul 4, 2006

Jun 25, 2004

10/877299

David Suitwai Ma - Cary NC, US

Infineon Technologies AG - Munich

G01R 31/02
H05K 1/11

324765, 324754, 324758, 439 66

Apparatus and method for testing a device wafer having a plurality of devices formed thereon. One embodiment of the invention provides an interface wafer comprising a plurality of contact pads disposed on a first surface for contacting a plurality of device pads on the device wafer and a plurality of interface pads disposed on a second surface for contacting probe needles on a probe card, wherein the plurality of interface pads are electrically connected to the plurality of contact pads and wherein the plurality of interface pads are disposed in a relaxed-pitch arrangement as compared to the plurality of contact pads.

7079441, Jul 18, 2006

Feb 4, 2005

11/049857

Torsten Partsch - Raleigh NC, US
David Ma - Cary NC, US

Infineon Technologies AG - Munich

G11C 7/00

365226, 365227, 365228

A power down is implemented in a memory device capable of performing a read operation in which data and a data strobe signal are supplied as outputs. The power down techniques includes generating a first signal for preventing the data from being supplied as an output of the memory device, generating a second signal for causing the data strobe signal to remain in a predetermined state, and generating a third signal for preventing the data strobe signal in the predetermined state from being supplied as an output of the memory device.