David L Mayhew, 4660 Sheridan St, Boston, MA 02130

6996658, Feb 7, 2006

May 21, 2002

10/152656

Lynne M. Brocco - Cambridge MA, US
Todd R. Comins - Chelmsford MA, US
Nathan J. Dohm - Natick MA, US
David E. Mayhew - Northborough MA, US
Carey J. McMaster - Stow MA, US

StarGen Technologies, Inc. - Marlborough MA

G06F 13/00

710312, 710315

The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric. More specifically, there is provided a device accessible by a host processor for expanding access over a first bus to a second bus, the first bus and the second bus each being adapted to separately connect to respective ones of a plurality of bus-compatible devices, each device which comprise a link, a first circuit adapted to couple between the first bus and the link, and a second circuit adapted to couple between the link and the second bus, the first circuit and the second circuit each being operated as a bridge and being operable to (a) send outgoing information serially through said link in a form different from that of the first bus and the second bus (b) approve an initial exchange between the first bus and the second bus in response to pending bus transactions having a characteristic signifying a destination across a device, and (c) allow the host processor, communicating through the first bus, to individually address different selectable ones of the bus-compatible devices on the second bus: (i) using on the first bus substantially the same type of addressing as is used to access devices on the first bus, and (ii) without first employing a second, intervening one of the bus-compatible devices on the second bus.

7062581, Jun 13, 2006

Sep 21, 2004

10/945615

Lynne M. Brocco - Cambridge MA, US
Todd R. Comins - Chelmsford MA, US
Nathan J. Dohm - Natick MA, US
David E. Mayhew - Northborough MA, US
Carey J. McMaster - Stow MA, US

StarGen Technologies, Inc. - Marlboro MA

G06F 13/00

710104, 710316, 370338, 370401, 709224

The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric. More specifically, there is provided a device accessible by a host processor for expanding access over a first bus to a second bus, the first bus and the second bus each being adapted to separately connect to respective ones of a plurality of bus-compatible devices, each device which comprise a link, a first circuit adapted to couple between the first bus and the link, and a second circuit adapted to couple between the link and the second bus, the first circuit and the second circuit each being operated as a bridge and being operable to (a) send outgoing information serially through said link in a form different from that of the first bus and the second bus (b) approve an initial exchange between the first bus and the second bus in response to pending bus transactions having a characteristic signifying a destination across a device, and (c) allow the host processor, communicating through the first bus, to individually address different selectable ones of the bus-compatible devices on the second bus: (i) using on the first bus substantially the same type of addressing as is used to access devices on the first bus, and (ii) without first employing a second, intervening one of the bus-compatible devices on the second bus.

7146452, Dec 5, 2006

Nov 12, 2005

11/271273

Lynne M. Brocco - Cambridge MA, US
Todd R. Comins - Chelmsford MA, US
Nathan J. Dohm - Natick MA, US
David E. Mayhew - Northborough MA, US
Carey J. McMaster - Stow MA, US

StarGen Technologies, Inc. - Marlborough MA

G06F 13/00

710312, 710315

The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric. More specifically, there is provided a device accessible by a host processor for expanding access over a first bus to a second bus, the first bus and the second bus each being adapted to separately connect to respective ones of a plurality of bus-compatible devices, each device which comprise a link, a first circuit adapted to couple between the first bus and the link, and a second circuit adapted to couple between the link and the second bus, the first circuit and the second circuit each being operated as a bridge and being operable to (a) send outgoing information serially through said link in a form different from that of the first bus and the second bus (b) approve an initial exchange between the first bus and the second bus in response to pending bus transactions having a characteristic signifying a destination across a device, and (c) allow the host processor, communicating through the first bus, to individually address different selectable ones of the bus-compatible devices on the second bus: (i) using on the first bus substantially the same type of addressing as is used to access devices on the first bus, and (ii) without first employing a second, intervening one of the bus-compatible devices on the second bus.

7443869, Oct 28, 2008

Dec 23, 2003

10/745737

Gary A. Solomon - Acton MA, US
Edward Butler - Chandler AZ, US
Joseph A. Schaefer - Chandler AZ, US
David E. Mayhew - Northborough MA, US
Todd R. Comins - Chelmsford MA, US
Lynne M. Brocco - Cambridge MA, US

Intel Corporation - Santa Clara CA

G06F 13/38

370412, 710 52

A queuing mechanism is described for managing packets between agents of a computer system. The queuing mechanism includes an ordered queue including a plurality of queue registers to store a plurality of packets. The queuing mechanism also includes a bypass queue coupled to the ordered queue, wherein, if a packet at head of the ordered queue is a delayed request and is stalled for lack of flow control credit, then the stalled packet is moved into the bypass queue.

7646760, Jan 12, 2010

Sep 21, 2004

10/945633

Lynne M. Brocco - Cambridge MA, US
Todd R. Comins - Chelmsford MA, US
Nathan J. Dohm - Natick MA, US
David E. Mayhew - Northborough MA, US
Carey J. McMaster - Stow MA, US

H04L 12/28
H04L 12/56

370351, 370389

A system and method for routing data elements from an origin to a terminus is disclosed. The switches each have a plurality of ports. These ports are numbered relative to one another, such that a first output port, adjacent to the input port, may be numbered “0”, while a second output port, adjacent to the first output port, would be numbered “1”, This numbering continues for each port in the switch. When a data element is received on an input port of the switch, an output port is selected based on a value contained in that received data element. In one embodiment, the value is contained within a path specification, which includes a count field and a plurality of turn fields.

8006024, Aug 23, 2011

Dec 21, 2009

12/643385

Lynne M. Brocco - Cambridge MA, US
Todd R. Comins - Chelmsford MA, US
Nathan J. Dohm - Natick MA, US
David E. Mayhew - Northborough MA, US
Carey J. McMaster - Stow MA, US

Jinsalas Solutions, LLC - Dover DE

G06F 13/00

710315, 710306

The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric. More specifically, there is provided a device accessible by a host processor for expanding access over a first bus to a second bus, the first bus and the second bus each being adapted to separately connect to respective ones of a plurality of bus-compatible devices, each device which comprise a link, a first circuit adapted to couple between the first bus and the link, and a second circuit adapted to couple between the link and the second bus, the first circuit and the second circuit each being operated as a bridge and being operable to (a) send outgoing information serially through said link in a form different from that of the first bus and the second bus (b) approve an initial exchange between the first bus and the second bus in response to pending bus transactions having a characteristic signifying a destination across a device, and (c) allow the host processor, communicating through the first bus, to individually address different selectable ones of the bus-compatible devices on the second bus: (i) using on the first bus substantially the same type of addressing as is used to access devices on the first bus, and (ii) without first employing a second, intervening one of the bus-compatible devices on the second bus.

8402197, Mar 19, 2013

Aug 22, 2011

13/215011

Lynne M. Brocco - Cambridge MA, US
Todd R. Comins - Chelmsford MA, US
Nathan J. Dohm - Natick MA, US
David E. Mayhew - Northborough MA, US
Carey J. McMaster - Stow MA, US

Jinsalas Solutions, LLC - Dover DE

G06F 13/00

710315, 710306

A method and structure(s) for providing a data path between and among nodes and processing elements within an interconnection fabric are described. More specifically, a device comprising a first circuit configured to couple between a first bus and a link is described. The circuit may be configured to operate as a bridge, support PCI configuration cycles, send outgoing information serially through the link in a format different from that of the first bus, and allow a host processor, communicating through the first bus, to selectively address one or more remote devices to which the device is configured to allow access. In some embodiments, the first circuit may support “spoof-proof” data protocols, and the device may operate in multiple modes including root bridge, leaf bridge, and gateway mode. Multiple addressing models may also be used.

2013029, Nov 7, 2013

Mar 18, 2013

13/846515

Todd R. Comins - Chelmsford MA, US
Nathan J. Dohm - Natick MA, US
David E. Mayhew - Northborough MA, US
Carey J. McMaster - Stow MA, US

G06F 13/40

710316

A fabric interconnect system may provide a data path between nodes and/or processing elements within an interconnection fabric. Identifiers may be assigned to particular components associated with the interconnection fabric. These identifiers may uniquely identify the particular components, and may indicate a path between a root node and a particular component. In some embodiments, the identifiers include turn counts and turn values that specify a turn-based bath from the root node to a particular component. One or more identifier acceptance rules may be used in order to determine whether a given component should accept and store a particular identifier that the component receives. For example, a lower priority identifier may be discarded in favor of a higher priority identifier.