David Nack resumes & CV records
Resumes
David Nack
David Nack
Location:
Orange County, California Area
Industry:
Semiconductors
David S Nack Deceased22806 Maiden Ln, San Juan Capistrano, CA 92692
David Nack Phones & Addresses
22806 Maiden Ln, Mission Viejo, CA 92692
Saint Louis, MO
Sacramento, CA
403 Kingston Ct, Roseville, CA 95661
Paradise Valley, AZ
Carmichael, CA
San Jose, CA
Orange, CA
Mentions for David S Nack
Publications & IP owners
Us Patents
Cmos Circuit For Maintaining A Constant Slew Rate
US Patent:
6501292, Dec 31, 2002
Filed:
Mar 2, 2000
Appl. No.:
09/517783
Inventors:
David S. Nack - Roseville CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 1716
US Classification:
326 27, 326 83, 326 86
Abstract:
A CMOS circuit maintains a constant slew rate over a range of environmental or process conditions. The circuit includes an output stage having a slew rate that is a function of the switching characteristic of the output stage and a bias current. A current adjustment stage adjusts the bias current in view of the switching characteristic to maintain a substantially constant slew rate. The slew rate of the output stage may be tuned to a desired level. A clamp may also be used to limit the voltage variations at the output stage.
Single Ended Controlled Current Source
US Patent:
6891428, May 10, 2005
Filed:
Nov 28, 2003
Appl. No.:
10/722544
Inventors:
Oleksiy Zabroda - Sacramento CA, US
David S. Nack - Mission Viejo CA, US
David S. Nack - Mission Viejo CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G05F001/10
US Classification:
327543
Abstract:
An apparatus and method for a controlled current source are provided. The apparatus may include at least one current cell. Each current cell includes first, second and third transistors. The first transistor can be configured as a switch transistor. The second transistor can be configured as a current controller and can be coupled in series with the first transistor. The third transistor has a gate and a substrate coupled to a gate and a substrate of the second transistor, respectively. The drain and source of the third transistor can be coupled to a second input configured to receive a second signal that is a compliment of a first signal received at an input of the first transistor.
Integrated Circuit Powered With Link Pulse Energy
US Patent:
2004021, Oct 28, 2004
Filed:
Apr 22, 2003
Appl. No.:
10/420177
Inventors:
David Nack - Roseville CA, US
International Classification:
H04L012/26
US Classification:
370/249000
Abstract:
According to some embodiments, an integrated circuit is powered with link pulse energy.
Amplitude Selection
US Patent:
2004022, Nov 4, 2004
Filed:
Mar 25, 2003
Appl. No.:
10/397947
Inventors:
David Nack - Roseville CA, US
International Classification:
G06F011/00
US Classification:
714/745000
Abstract:
In one embodiment, a method is provided. In the method of this embodiment, a first range of amplitudes may be selected from a plurality of ranges of amplitudes. The first range of amplitudes may include a first amplitude of a signal received via a communication medium. The method of this embodiment may also include selecting a second amplitude of a signal to be transmitted via the communication medium. The second amplitude may be included in a second range of amplitudes included in the plurality of ranges of amplitudes. The second amplitude may be selected based, at least in part, upon the selected first range of amplitudes. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
Modified Third Order Phase-Locked Loop
US Patent:
6188739, Feb 13, 2001
Filed:
Oct 21, 1997
Appl. No.:
8/954914
Inventors:
James W. Everitt - Granite Bay CA
David S. Nack - Roseville CA
James Parker - Rancho Cordova CA
David S. Nack - Roseville CA
James Parker - Rancho Cordova CA
Assignee:
Level One Communications, Inc. - Sacramento CA
International Classification:
H03D 324
H03L 706
H03L 706
US Classification:
375376
Abstract:
A phase-locked loop circuit is disclosed which exhibits a wide capture range and a low quality factor (Q) to prevent ringing and improve stability without adding area, increasing power consumption or increasing noise levels. The phase-locked loop includes a comparator to generate an error signal, an oscillator which generates an output signal in response to a control signal and a loop filter which generates the control signal based on the error signal. The loop filter includes a first integrator operatively coupled through a threshold limit detector to a second integrator. The threshold limit detector supplies an electric charge to the second integrator only when the first integrator is proximate to either an upper limit or a lower limit of the first integrator's operating range. The oscillator generates the output signal which tracks the input reference signal frequency as an integer multiple of the input reference signal frequency. The oscillator generates the output signal in response to varying current levels of the control signal.
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