David Lynn Peart, 58107 Palace Hotel Ln, Goshen, VA 24439

6624659, Sep 23, 2003

Jun 30, 2000

09/608529

Isaac P. Abraham - Kent WA
David R. Johnson - Olympia WA
Jed Griffin - Olympia WA
David Peart - Olympia WA

Intel Corporation - Santa Clara CA

H03K 190175

326 82, 326 83, 326 30

In one embodiment of the invention, an update circuit having a bus driver to drive a bus dynamically receives an update compensation code. The bus driver receives data at a data clock signal. The update compensation code controls impedance matching at the bus driver according to the data. A code generator generates the update compensation code at a base clock signal. The base clock signal is synchronized with the data clock signal. The base clock signal has an update interval and a quiet interval. A distribution ring interface distributes the update compensation code to the update circuit synchronously with the base clock signal.

8181145, May 15, 2012

Mar 11, 2009

12/402246

Kester B. Rice - Monument CO, US
David L. Peart - Round Rock TX, US

Synopsys, Inc. - Mountain View CA

G06F 17/50
G06F 9/455

716134, 716132, 716133, 716135, 716139

One embodiment provides a system comprising methods and apparatuses that generate a floorplan for a hierarchical circuit design. More specifically, the system can receive a non-reduced netlist description for the hierarchical circuit design, and generate a reduced netlist which includes the interface logic elements of the netlist. The system can then generate the floorplan by using the reduced netlist as input. Note that the amount of computational resources and time required to generate a floorplan is substantially reduced because the system generates the floorplan using the reduced netlist instead of using the non-reduced netlist.

8612913, Dec 17, 2013

Dec 21, 2012

13/725725

David Peart - Round Rock TX, US

Synopsys, Inc. - Mountain View CA

G06F 9/455
G06F 17/50

716113, 716108, 716111, 716112, 716126, 716130, 703 19

A method and apparatus for determining the propagation delay of a selected net in a circuit design is described. In one exemplary embodiment, a selected net is received, where the selected net includes a plurality of characteristics that represent the physical and/or parasitic parameters of the net. A net is a set of one or more wires that connects a set of circuit junctions between a pair of endpoints of that net. In addition, a simulation is performed on the selected net using the plurality of characteristics. The circuit design system computes the propagation delay for the selected net based on the simulation and makes available the propagation delay of that net. The propagation delay for a net is the delay for a signal traveling between the endpoints of the net.

2016026, Sep 15, 2016

Sep 21, 2015

14/860636

- Mountain View CA, US
David L. Peart - Round Rock TX, US
Jeffrey Jude Loescher - Portland OR, US

G06F 17/50

A method of establishing regions for placing cells of an integrated circuit (IC) includes, in part, assigning a precedence value to each of a multitude of constraint regions of the IC, and forming a multitude regions each associated with one of the constraint regions. The region associated with each constraint region is formed in accordance with the precedence value of its associated constraint region and the precedence values associated with any other constraint regions overlapping the first constraint region. Each region in a subset of the constraint regions is further defined in accordance with the region's transparency/opacity attribute.

2015025, Sep 10, 2015

May 27, 2015

14/723354

- Mountain View CA, US
David L. Peart - Round Rock TX, US
Luis D. Guilin - Livermore CA, US
Jeffrey J. Loescher - Portland OR, US

G06F 17/50

Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in _a circuit design layout in response to modifying the circuit design layout. Some embodiments substantially instantaneously update pin locations of a block or partition in response to changing the size or shape of the block or partition. Some embodiments enable a user to view a circuit design layout based on the logical hierarchy, and also based on at least one additional attribute type such as voltage, power, or clock domain.

2014018, Jul 3, 2014

Dec 27, 2012

13/728873

- Mountain View CA, US
David L. Peart - Round Rock TX, US
Russell Segal - Mountain View CA, US
Douglas Chang - San Jose CA, US
Ksenia Roze - Mountain View CA, US

SYNOPSYS, INC. - Mountain View CA

G06F 17/50

716102

Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the circuit design layout. Some embodiments substantially instantaneously update pin locations of a block or partition in response to changing the size or shape of the block or partition. Some embodiments enable a user to view a circuit design layout based on the logical hierarchy, and also based on at least one additional attribute type such as voltage, power, or clock domain.