David A Penry, 56551 E Sheffield Ave, Gilbert, AZ 85296

5894587, Apr 13, 1999

Jun 30, 1997

8/884847

Kevin Normoyle - Santa Clara CA
David Penry - Sunnyvale CA
Jui-Cheng Su - Sunnyvale CA

Sun Microsystems, Inc. - Palo Alto CA

G06F 1300

395306

A system for maintaining completion order in a multiple bus system including a bridge that posts write data includes logic units for implementing a DRAIN/EMPTY protocol. A bridge logic unit asserts an EMPTY signal when the secondary posting buffers are empty. Interrupt processing is delayed until the EMPTY signal is asserted thereby assuring that all writes are completed. If an interrupt is received and the EMPTY signal is not asserted then a DRAIN signal is asserted while the EMPTY signal is not asserted. The bridge retries all upstream write requests until EMPTY is asserted.

6003104, Dec 14, 1999

Dec 31, 1997

9/002014

Gunes Aybay - Sunnyvale CA
Sandeep Aggarwal - Santa Cruz CA
David Penry - Sunnyvale CA

Sun Microsystems, Inc. - Palo Alto CA

G06F 1340
G06F 1338
G06F 13364

710126

A CPU of a microprocessor includes a common bus, a bus interface unit (BIU), and a plurality of module units. The BIU has a plurality of first ports coupled to respective first ports of the module units via dedicated buses therebetween and has a second port coupled to a first port of the common bus. The module units each include a second port coupled to respective second ports of the common bus. Communication between the module units is routed through and controlled by the BIU. To request a transaction, a module unit (the initiator) sends a request to the BIU via its dedicated bus to the BIU. The BIU arbitrates among present requests and, in response thereto, grants the arbitration winner's request and transmits a command to the target of the requested transaction. Preferably, both of these signals being are transmitted via the dedicated buses. Thereafter, data is routed from, for instance, the target, to the BIU via a corresponding dedicated bus.

5944808, Aug 31, 1999

Jan 31, 1997

8/792892

David A. Penry - San Jose CA

Sun Microsystems, Inc. - Palo Alto CA

G06F 1300

710129

A PCI-to-PCI bridge circuit configurable to pass a parity error from one bus to the other bus during a prefetch includes a first interface for interfacing with a first PCI bus, a second interface for interfacing with to a second PCI bus, and a parity correction logic circuit. In response to one of a set of predetermined read commands from a device on the first PCI bus to read data from a device on the second PCI bus, the bridge circuit will initiate a prefetch transaction on the second PCI bus to read the requested data from the device on the second PCI bus. The parity correction logic circuit is coupled to receive from the first interface a first byte enable signal and a second byte enable signal, which are part of the read transaction on the first PCI bus. The parity correction logic circuit is also coupled to receive from the second interface a parity signal corresponding to the prefetch transaction on the second PCI bus. The parity correction logic circuit provides to the first interface a parity signal that causes a data parity error for the read transaction on said first PCI bus when the prefetch read transaction on said second PCI bus has a data parity error.

6100732, Aug 8, 2000

Jun 20, 1997

8/879559

David A. Penry - Sunnyvale CA
Kevin B. Normoyle - Santa Clara CA

Sun Microsystems, Inc. - Palo Alto CA

H04L 700

327144

A phase-enable circuit clocks a first functional unit at a first frequency and a second functional unit at a second frequency. Each of the first and second functional units is provided with a first clock signal of the first frequency. A phase-enable generator then uses the first clock signal and a second clock signal of a second frequency lower than the first frequency to develop a phase-enable signal that periodically disables a clock input terminal of the second functional unit so that the second functional unit is clocked at the second frequency. Changing the frequency of the second clock to zero switches the phase-enable circuit into another mode of operation. In that mode, the clock input terminal of the second functional unit is constantly enabled and the first and second functional units are each clocked at the first frequency.