David Bernard Resnick, 557601 Pacific Willow Dr, Tucson, AZ 85747

7565593, Jul 21, 2009

Nov 10, 2006

11/558454

R. Paul Dixon - Carrollton TX, US
David R. Resnick - Tucson AZ, US
Van L. Snyder - Eau Claire WI, US

Cray Inc. - Seattle WA

H03M 13/00

714754

A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

7676728, Mar 9, 2010

Nov 10, 2006

11/558452

David R. Resnick - Tucson AZ, US
Van L. Snyder - Eau Claire WI, US
Michael F. Higgins - Eau Claire WI, US
Alan M. Grossmeier - Chippewa Falls WI, US
Kelly J. Marquardt - Eau Claire WI, US
Gerald A. Schwoerer - Chippewa Falls WI, US

Cray Inc. - Seattle WA

G11C 29/00

714764, 711105, 711154

A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

7826996, Nov 2, 2010

Feb 26, 2007

11/679175

David R. Resnick - Tucson AZ, US
Gerald A. Schwoerer - Chippewa Falls WI, US
Kelly J. Marquardt - Eau Claire WI, US
Alan M. Grossmeier - Chippewa Falls WI, US
Michael L. Steinberger - Chippewa Falls WI, US
Van L. Snyder - Eau Claire WI, US
Roger A. Bethard - Chippewa Falls WI, US

Cray Inc. - Seattle WA

G01C 31/00
G06F 11/00

702118, 702188, 702189, 702190

A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e. g. , the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.

8024638, Sep 20, 2011

Nov 10, 2006

11/558450

David R. Resnick - Tucson AZ, US
Van L. Snyder - Eau Claire WI, US
Michael F. Higgins - Eau Claire WI, US

Cray Inc. - Seattle WA

H03M 13/00

714758, 36518904

A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

8126674, Feb 28, 2012

Aug 27, 2010

12/870516

David R. Resnick - Tucson AZ, US
Gerald A. Schwoerer - Chippewa Falls WI, US
Kelly J. Marquardt - Eau Claire WI, US
Alan M. Grossmeier - Colfax WI, US
Michael L. Steinberger - Chippewa Falls WI, US
Van L. Snyder - Eau Claire WI, US
Roger A. Bethard - Chippewa Falls WI, US

Cray Inc. - Seattle WA

G01R 31/14
G01R 31/00

702118, 702119, 702120, 702121

A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e. g. , the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.

8566684, Oct 22, 2013

May 26, 2011

13/116976

H. Lee Ward - Albuquerque NM, US
Anand Ganti - Albuquerque NM, US
David R. Resnick - Tucson AZ, US

Sandia Corporation - Albuquerque NM
Micron Technology, Inc. - Boise ID

H03M 13/03

714796, 714758, 714777

A plurality of columns for a check matrix that implements a distance d linear error correcting code are populated by providing a set of vectors from which to populate the columns, and applying to the set of vectors a filter operation that reduces the set by eliminating therefrom all vectors that would, if used to populate the columns, prevent the check matrix from satisfying a column-wise linear independence requirement associated with check matrices of distance d linear codes. One of the vectors from the reduced set may then be selected to populate one of the columns. The filtering and selecting repeats iteratively until either all of the columns are populated or the number of currently unpopulated columns exceeds the number of vectors in the reduced set. Columns for the check matrix may be processed to reduce the amount of logic needed to implement the check matrix in circuit logic.

2018034, Nov 29, 2018

Jul 16, 2018

16/036177

- Boise ID, US
David Resnick - Tucson AZ, US

Micron Technology, Inc. - Boise ID

G11C 7/10
G06F 15/80
G06F 9/30
G06F 15/78
G11C 7/22

Memories and methods for performing an atomic memory operation are disclosed, including a memory having a memory store, operation logic, and a command decoder. Operation logic can be configured to receive data and perform operations thereon in accordance with internal control signals. A command decoder can be configured to receive command packets having at least a memory command portion in which a memory command is provided and data configuration portion in which configuration information related to data associated with a command packet is provided. The command decoder is further configured to generate a command control signal based at least in part on the memory command and further configured to generate control signal based at least in part on the configuration information.

2018023, Aug 16, 2018

Apr 6, 2018

15/946957

- Boise ID, US
David Resnick - Tuscon AZ, US

Micron Technology, Inc. - Boise ID

G11C 14/00
G06F 12/02

A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. More particularly, the system reads data from a bank of memory cells or cache memory, performs a logic function on the data to produce results data, and writes the results data back to the bank or the cache memory. The logic function may be a Boolean logic function or some other logic function.