David B Schuck, 813328 Amherst Way, Eugene, OR 97408

4417334, Nov 22, 1983

Apr 16, 1981

6/254792

Robert O. Gunderson - Poway CA
James E. Kocol - Escondido CA
David B. Schuck - Escondido CA

NCR Corporation - Dayton OH

H04J 600

370 85

A data processing system employing broadcast packet switching and having a plurality of subsystems and a system bus for linking the subsystems. The subsystems are grouped within stations that are each enclosed by a computer cabinet. The system bus includes a star coupler, first and second external transmission lines connecting each station to the star coupler, and first and second internal transmission lines within each station that are coupled to the first and second external transmission lines. The subsystems within each station are each coupled to the first and second internal transmission lines by a system bus interface. The system bus interface monitors the system bus for an idle condition, and passes a message from its subsystem to the system bus only when it detects an idle condition on the system bus. Each message on the system bus includes a postamble that is garbled by any system bus interface that detects an error in any message on the system bus. Each subsystem has a local memory that includes a mailbox for storing header information of messages that are to be copied by that subsystem.

4400049, Aug 23, 1983

Aug 12, 1981

6/292309

David B. Schuck - Escondido CA

NCR Corporation - Dayton OH

H01R 1362

339176MP

A connector for connecting coplanar circuit boards in an edge-to-edge fashion. The connector has a housing with a circuit board receiving cavity extending through and between opposite faces of the housing. The cavity has two opposing side walls which support electrical terminals for contacting conductors on the edges of circuit boards that are inserted into the cavity at the opposing faces of the housing. A passage extends transversely through the housing and intersects the cavity and receives a pin for engaging the terminals and maintaining them fixed within the housing. The edge-to-edge connection of two or more coplanar circuit boards is provided by use of the connector.

4488354, Dec 18, 1984

Nov 16, 1981

6/321370

Kasun K. Chan - Del Mar CA
Gerald J. Erickson - San Diego CA
David B. Schuck - Escondido CA
James W. Stone - Escondido CA

NCR Corporation - Dayton OH

H05K 336
G01R 300
H01K 112

29830

A method and apparatus for simulating custom chips to be used in a data processing system. Each chip is simulated by a chip simulator that includes a mother board and a plurality of baby boards mounted and interconnected on the mother board. Each baby board has circuit components mounted thereon for performing the circuit function of one cell of the chip. Chip simulators are interconnected in an interconnecting apparatus that supports the mother boards in parallel and spaced apart relation. Chip simulators that represent all of the chips found on a single printed circuit board in the system are interconnected at the interconnecting apparatus so that design errors which are only evident when the chips are interconnected can be tested for and detected prior to fabrication of the chips.

4583161, Apr 15, 1986

Apr 16, 1981

6/255062

Robert O. Gunderson - Poway CA
James E. Kocol - Escondido CA
David B. Schuck - Escondido CA

NCR Corporation - Dayton OH

G06F 900

364200

A data processing system employing broadcast packet switching and having a plurality of subsystems and a system bus for linking the subsystems. The subsystems are grouped within stations that are each enclosed by a computer cabinet. The system bus includes a star coupler, first and second external transmission lines connecting each station to the star coupler, and first and second internal transmission lines within each station that are coupled to the first and second external transmission lines. The subsystems within each station are each coupled to the first and second internal transmission lines by a system bus interface. The system bus interface monitors the system bus for an idle condition, and passes a message from its subsystem to the system bus only when it detects an idle condition on the system bus. Each message on the system bus includes a postamble that is garbled by any system bus interface that detects an error in any message on the system bus. Each subsystem has a local memory that includes a mailbox for storing header information of messages that are to be copied by that subsystem.

4494185, Jan 15, 1985

Apr 16, 1981

6/254850

Robert O. Gunderson - Poway CA
James C. Kocol - Escondido CA
David B. Schuck - Escondido CA

NCR Corporation - Dayton OH

G06F 1300

364200

A data processing system employing broadcast packet switching and having a plurality of subsystems and a system bus for linking the subsystems. The subsystems are grouped within stations that are each enclosed by a computer cabinet. The system bus includes a star coupler, first and second external transmission lines connecting each station to the star coupler, and first and second internal transmission lines within each station that are coupled to the first and second external transmission lines. The subsystems within each station are each coupled to the first and second internal transmission lines by a system bus interface. The system bus interface monitors the system bus for an idle condition, and passes a message from its subsystem to the system bus only when it detects an idle condition on the system bus. Each message on the system bus includes a postamble that is garbled by any system bus interface that detects an error in any message on the system bus. Each subsystem has a local memory that includes a mailbox for storing header information of messages that are to be copied by that subsystem.

4319356, Mar 9, 1982

Dec 19, 1979

6/105185

James E. Kocol - Escondido CA
David B. Schuck - Escondido CA

NCR Corporation - Dayton OH

G06F 1110

371 38

A self-correcting memory system includes internal error detection and correction circuitry that periodically accesses each data word and a group of ECC check bits associated with each data word stored in the memory system. The error detection and correction circuitry includes an ECC checking circuit that receives the accessed data word, generates ECC bits, and compares those ECC bits to the group of ECC check bits associated with the data word. The resulting signal is used to correct any single bit in error, and to indicate the presence of a double bit error. A self-correct address counter is cascaded to a refresh address counter in the control circuitry of the memory system so that the accessing of each data word occurs during a refresh cycle of the memory system.

4305124, Dec 8, 1981

Sep 26, 1979

6/079027

Daniel J. Marro - Escondido CA
David B. Schuck - Escondido CA

NCR Corporation - Dayton OH

G06F 700

364200

A pipelined computer which executes high level language instructions is disclosed. The pipelined computer includes a memory for storing the high level language instructions therein. A plurality of microprogrammed digital computers are coupled in parallel to the memory, and are also intercoupled via an interlocking bus. The microprogrammed computers, in conjunction with the interlocking bus, form a pipeline for executing the high level language instructions. Each of the computers is a separately microprogrammable stage of the pipeline.

4148558, Apr 10, 1979

Oct 17, 1977

5/842869

David B. Schuck - Escondido CA

NCR Corporation - Dayton OH

G02B 514

350 9620

An optical by-pass relay for use with an optical transmission line wherein transmitted optical energy is focused on a light detector for conversion into an electrical signal which electrical signal is coupled to a utilization device. A light emitter coupled to the utilization device, transmits lights onto the transmission line to thereby place the utilization device into the optical transmission line. Means are provided for displacing the detector and emitter from the optical path of the transmission line and for positioning an optical coupler such as a glass rod into the optical path to thereby by-pass the utilization device while providing continuity to the optical signal traversing the optical transmission line.