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David V Venables, 64619 Torrington Dr, Sunnyvale, CA 94087

David Venables Phones & Addresses

619 Torrington Dr, Sunnyvale, CA 94087    408-7392402   

1000 Escalon Ave, Sunnyvale, CA 94085    408-7392402   

38824 Stillwater Cmn, Fremont, CA 94536    510-7909925   

Union City, CA   

Somerville, MA   

Indian Rocks Beach, FL   

Gainesville, FL   

Jacksonville, FL   

Santa Clara, CA   

Largo, FL   

619 Torrington Dr, Sunnyvale, CA 94087    510-7909925   

Work

Position: Building and Grounds Cleaning and Maintenance Occupations

Education

Degree: High school graduate or higher

Mentions for David V Venables

Resumes & CV records

Resumes

David Venables Photo 24

David Venables

David Venables Photo 25

David Venables

David Venables Photo 26

David Venables

David Venables Photo 27

David Venables

Location:
United States
David Venables Photo 28

David Venables

Location:
United States

Publications & IP owners

Us Patents

Photodiode With High Esd Threshold

US Patent:
7948006, May 24, 2011
Filed:
Jun 1, 2009
Appl. No.:
12/476070
Inventors:
Zhong Pan - San Jose CA, US
David Venables - Sunnyvale CA, US
Assignee:
JDS Uniphase Corporation - Milpitas CA
International Classification:
H01L 23/60
US Classification:
257173, 257452, 257458, 257656, 257459, 257461, 257E31061, 257E29336, 257E3111
Abstract:
A photodetector with an improved electrostatic discharge damage threshold is disclosed, suitable for applications in telecommunication systems operating at elevated data rates. The photodetector may be a PIN or an APD fabricated in the InP compound semiconductor system. The increased ESD damage threshold is achieved by reducing the ESD induced current density in the photodetector by a suitable widening of the contact at a critical location, increasing the series resistance and promoting lateral current spreading by means of a current spreading layer.

Avalanche Photodiode With Edge Breakdown Suppression

US Patent:
2009002, Jan 22, 2009
Filed:
Jul 15, 2008
Appl. No.:
12/173189
Inventors:
Zhong Pan - San Jose CA, US
David Venables - Sunnyvale CA, US
Craig Ciesla - Mountain View CA, US
Assignee:
JDS Uniphase Corporation - Milpitas CA
International Classification:
H01L 31/0336
H01L 31/18
US Classification:
257185, 438 87, 257E31005
Abstract:
The invention relates to an avalanche photodiode having enhanced gain uniformity enabled by a tailored diffused p-n junction profile. The tailoring is achieved by a two stage doping process incorporating a solid source diffusion in combination with conventional gas source diffusion. The solid source diffusion material is selected for its solubility to the dopant compared to the solubility of the multiplication layer to dopant. The solid source has a diameter between the first and second diffusion windows. Thus, there are three distinct diffusion regions during the second diffusion. The dopant in the multiplication layer at the edge region, the dopant from the solid source material with a relatively higher dopant concentration (limited by the solubility of the dopant in the solid source material) at the intermediate region, and the central region exposed to an infinite diffusion source from the solid source material as it is continually charged with new dopant from the external gas source. The result is that both the dopant concentration and the diffusion depth decrease gradually from the center to the edge of the device. This tailored diffusion profile enables control of the electric field distribution such that edge breakdown is suppressed.

Trenches For Increasing A Quantity Of Reliable Chips Produced From A Wafer

US Patent:
2019028, Sep 19, 2019
Filed:
Mar 16, 2018
Appl. No.:
15/923801
Inventors:
- Milpitas CA, US
Victor Rossin - Milpitas CA, US
David Venables - Milpitas CA, US
Jingcong Wang - Milpitas CA, US
International Classification:
H01L 29/32
H01S 5/24
H01S 5/02
H01L 21/762
H01S 5/183
H01L 29/06
H01L 21/82
H01L 21/3065
H01L 21/66
H01L 21/306
Abstract:
A light-emitting device may comprise a set of layers comprising a substrate layer, and a set of epitaxial layers deposited on the substrate layer. The set of epitaxial layers may include a strained layer. The strained layer may include a set of active zones to be used to generate optical gain. The light-emitting device may comprise a set of trenches etched into a subset of the set of layers of the light-emitting device. The set of trenches may prevent a set of defects or dislocations in a wafer from which the light-emitting device was formed from propagating into the set of active zones.

Configuring An Emitter Pattern For An Emitter Array To Avoid A Potential Dislocation Line

US Patent:
2019014, May 16, 2019
Filed:
Sep 28, 2018
Appl. No.:
16/146180
Inventors:
- Milpitas CA, US
David Venables - Milpitas CA, US
Eric R. Hegblom - Sunnyvale CA, US
Ajit Vijay Barve - San Jose CA, US
International Classification:
H01S 5/42
H01S 5/183
Abstract:
A die may comprise a plurality of adjacent emitters and a potential dislocation line. The plurality of adjacent emitters and the potential dislocation line may be offset from each other within a range of angles based on a relative rotation of the plurality of adjacent emitters and the potential dislocation line.

Isbn (Books And Publications)

The Racing Fifteen-Hundreds: A History Of Voiturette Racing From 1931 To 1940

Author:
David Venables
ISBN #:
0851840248

Napier: The First To Wear The Green

Author:
David Venables
ISBN #:
0854299890

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