Dean R Batten, 572844 Edgemont Dr, Allentown, PA 18103

6859871, Feb 22, 2005

Oct 19, 1998

09/174936

Dean Batten - Allentown PA, US
Paul Gerard D'Arcy - Harleysville PA, US
C. John Glossner - Allentown PA, US
Sanjay Jinturkar - Bethlehem PA, US
Jesse Thilo - Bethlehem PA, US
Kent E. Wires - Phillipsburg NJ, US

Agere Systems Inc. - Allentown PA

G06F015/00

712208, 712219, 712233

The invention provides techniques for reducing the power consumption of pipelined processors. In an illustrative embodiment, the invention evaluates the predicates of predicated instructions in a decode stage of a pipelined processor, and annuls instructions with false predicates before those instructions can be processed by subsequent stages, e. g, by execute and writeback stages. The predicate dependencies can be handled using, e. g. , a virtual single-cycle execution technique which locks a predicate register while the register is in use by a given instruction, and then stalls subsequent instructions that depend on a value stored in the register until the register is unlocked. As another example, the predicate dependencies can be handled using a compiler-controlled dynamic dispatch (CCDD) technique, which identifies dependencies associated with a set of instructions during compilation of the instructions in a compiler. One or more instructions are then grouped in a code block which includes a field indicating the dependencies associated with those instructions, and the instructions are then, e. g. , either stalled or decoded serially, based on the dependencies present in the code block.

6317821, Nov 13, 2001

May 18, 1998

9/080787

Dean Batten - Allentown PA
Paul Gerard D'Arcy - Harleysville PA
C. John Glossner - Allentown PA
Sanjay Jinturkar - Bethlehem PA
Jesse Thilo - Bethlehem PA

Lucent Technologies Inc. - Murray Hill NJ

G06F 930

712200

A pipelined processor is configured to provide virtual single-cycle instruction execution using a register locking mechanism in conjunction with instruction stalling based on lock status. In an illustrative embodiment, a set of register locks is maintained in the form of a stored bit vector in which each bit indicates the current lock status of a corresponding register. A decode unit receives an instruction fetched from memory, and decodes the instruction to determine its source and destination registers. The instruction is stalled for at least one processor cycle if either its source register or destination register is already locked by another instruction. The stall continues until the source and destination registers of the instruction are both unlocked, i. e. , no longer in use by other instructions. Before the instruction is dispatched for execution, the destination register of the instruction is again locked, and remains locked until after the instruction completes execution and writes its result to the destination register.

6282585, Aug 28, 2001

Mar 22, 1999

9/274134

Dean Batten - Allentown PA
Paul Gerard D'Arcy - Alpharetta GA
C. John Glossner - Allentown PA
Sanjay Jinturkar - Bethlehem PA
Kent E. Wires - Bethlehem PA

Agere Systems Guardian Corp. - Orlando FL

G06F 1314

710 5

The invention provides techniques for reducing the port pressure of a clustered processor. In an illustrative embodiment, the processor includes multiple clusters of execution units, with each of the clusters having a portion of a register file and a portion of a predicate file associated therewith, such that a given cluster is permitted to write to and read from its associated portions of the register and predicate files. A cooperative interconnection technique in accordance with the invention utilizes an inter-cluster move instruction specifying a source cluster and a destination cluster to copy a value from the source cluster to the destination cluster. The value is transmitted over a designated interconnect structure within the processor, and the inter-cluster move instruction is separated into two sub-instructions, one of which is executed by a unit in the source cluster, and another of which is executed by a unit in the destination cluster. These units may be, e. g. , augmented ALUs or dedicated interface units within the clusters.

6256725, Jul 3, 2001

Dec 4, 1998

9/205466

Dean Batten - Allentown PA
Paul Gerard D'Arcy - Alpharetta GA
C. John Glossner - Allentown PA
Sanjay Jinturkar - Bethlehem PA
Jesse Thilo - Bethlehem PA
Kent E. Wires - Bethlehem PA

Agere Systems Guardian Corp. - Orlando FL

G06F 1202

712200

A processor is configured to include at least two architecturally-distinct storage spaces, such as, for example, a stack for storing control operands associated with one or more instructions, and a register file for storing computational operands associated with one or more instructions. The processor further includes a datapath which is at least partially shared by the stack and register file, a multiplexer operative to select an output of either the stack or the register file for application to an input of the shared datapath, and a demultiplexer operative to select an output of the shared datapath for application to an input of either the stack or the register file. A program executed by the processor selects one of the storage spaces using, for example, a tag bit associated with a given instruction and indicating which of the storage spaces is to be used with that instruction, or a branch machine view (bmv) instruction which generates a control signal operative to select the given one of the storage spaces.

6230251, May 8, 2001

Mar 22, 1999

9/274133

Dean Batten - Allentown PA
Paul Gerard D'Arcy - Alpharetta GA
C. John Glossner - Allentown PA
Sanjay Jinturkar - Bethlehem PA
Kent E. Wires - Bethlehem PA

Agere Systems Guardian Corp. - Maimi Lakes FL

G06F 1314

712 11

The invention provides techniques for reducing the port pressure of a clustered processor. In an illustrative embodiment, the processor includes multiple clusters of execution units, with each of the clusters having a portion of a register file and a portion of a predicate file associated therewith, such that a given cluster is permitted to write to and read from its associated portions of the register and predicate files. A replication technique in accordance with the invention reduces port pressure by replicating, e. g. , a register lock file and a predicate lock file of the processor for each of the clusters. The replicated files vary depending upon whether the technique is implemented with a write-only interconnection or a read-only interconnection.

6269437, Jul 31, 2001

Mar 22, 1999

9/274129

Dean Batten - Allentown PA
Paul Gerard D'Arcy - Alpharetta GA
C. John Glossner - Allentown PA
Sanjay Jinturkar - Bethlehem PA
Kent E. Wires - Bethlehem PA

Agere Systems Guardian Corp. - Orlando FL

G06F 1576
G06F 1336
G06F 15167

712 28

The invention provides techniques for reducing the port pressure of a clustered processor. In an illustrative embodiment, the processor includes multiple clusters of execution units, with each of the clusters having a portion of a register file and a portion of a predicate file associated therewith, such that a given cluster is permitted to write to and read from its associated portions of the register and predicate files. A duplicator interconnection technique in accordance with the invention reduces port pressure by providing one or more global move units in the processor. A given global move unit uses an inter-cluster move instruction to copy a value from a portion of the register or predicate file associated with a source cluster to another portion of the register or predicate file associated with a destination cluster.

6260189, Jul 10, 2001

Sep 14, 1998

9/152744

Dean Batten - Allentown PA
Paul Gerard D'Arcy - Harleysville PA
C. John Glossner - Allentown PA
Sanjay Jinturkar - Bethlehem PA
Jesse Thilo - Bethlehem PA
Stamatis Vassiliadis - Pijnacker, NL
Kent E. Wires - Phillipsburg NJ

Lucent Technologies Inc. - Murray Hill NJ

G06F 944

717 6

The invention provides techniques for improving the performance of pipelined processors by eliminating unnecessary stalling of instructions. In an illustrative embodiment, a compiler is used to identify pipeline dependencies in a given set of instructions. The compiler then groups the set of instructions into a code block having a field which indicates the types of pipeline dependencies, if any, in the set of instructions. The field may indicate the types of pipeline dependencies by specifying which of a predetermined set of hazards arise in the plurality of instructions when executed on a given pipelined processor. For example, the field may indicate whether the code block includes any Read After Write (RAW) hazards, Write After Write (WAW) hazards or Write After Read (WAR) hazards. The code block may include one or more dynamic scheduling instructions, with each of the dynamic scheduling instructions including a set of instructions for execution in a multi-issue processor.