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Dejan C Jovanovic, 594737 N Winchester Ave UNIT 3N, Chicago, IL 60640

Dejan Jovanovic Phones & Addresses

Chicago, IL   

9400 Schug Cv, Austin, TX 78759    512-5270492    512-9921515   

Wheeling, IL   

123 San Mateo Rd, Santa Fe, NM 87505    505-9928589   

Plano, TX   

Dallas, TX   

Champaign, IL   

Palatine, IL   

Mentions for Dejan C Jovanovic

Dejan Jovanovic resumes & CV records

Resumes

Dejan Jovanovic Photo 37

Country Director At Link Consultants International | Experienced In Multinationals | Experienced Sales Manager | Fmcg

Position:
Country Director at Link Consultants International | Dale Carnegie Training, External Consultant at Vercon
Location:
Montenegro
Industry:
Human Resources
Work:
Link Consultants International | Dale Carnegie Training - Montenegro since Apr 2013
Country Director
Vercon - Montenegro since Jun 2012
External Consultant
Voli - Montenegro Jan 2012 - May 2012
Sales Manager for Carnex & Vindija division
Coca-Cola HBC - Podgorica Feb 2009 - Jan 2012
Regional Sales Manager for Montenegro
Coca-Cola HBC - Montenegro coast Sep 2006 - Feb 2009
Sales Supervisor for the South Region of Montenegro
Philip Morris International - Montenegro May 2005 - Sep 2006
Merchandiser for the South Region of Montenegro
Forte Mare Oct 2002 - May 2005
Manager
PIK Takovo - Gornji Milanovac Serbia Oct 1996 - Oct 2002
Sales Representative
PIK Takovo - Serbia and Montenegro Jun 1992 - Oct 1996
Warehouse Manager
Education:
BA in Economics,University of DOBA, Slovenia 2012 - 2014
BA in Economics, Business Administration and Management, General
Skills:
Contract Negotiation, FMCG, Merchandising, Key Account Management, Sales Management, Performance Management, Team Management, Partner Relationship, Cost Management, Planning, Key Account Development, Cost Reduction, Modern Trade, Strategic Planning, Business Planning, New Business Development, Negotiation, Coaching, Customer Relations, Change Management, Trade Marketing, Distributor Relations, Optimization, Forecasting, Cold Calling, Employee Training, Public Speaking, Recruiting, Strategy Execution, Analysis, Team Building, Team Leadership, Business Development
Interests:
Management training, new technology, fishing, tennis, squash, digital photography, community theater, professional networking, international travel
Honor & Awards:
KAMpion award winner (award winner in Key Account Management in the Coca Cola Hellenic group ), 2011
Languages:
English
Montenegrin
Serbian
Italian
Russian
Spanish
Dejan Jovanovic Photo 38

Managing Director At Swarovski Subotica

Position:
Managing Director at Swarovski
Location:
Other
Industry:
Packaging and Containers
Work:
Swarovski - Serbia since Jul 2013
Managing Director
Ball Packaging Europe Oct 2011 - Jul 2013
Operations Support Manager - Business Development
Ball Packaging Europe Sep 2008 - Nov 2011
Manufacturing Manager
Ball Packaging Europe Dec 2005 - Sep 2008
Production Manager
Ball Packaging Europe Jun 2005 - Dec 2005
Production Coordinator
Ball Packaging Europe Dec 2004 - Jun 2005
Shift Manager
Jugohemija FSA Grafopak Jun 2002 - Nov 2004
Engineering Supervisor
Education:
University of Belgrade 1992 - 2000
M.Sc., Mechanics
Skills:
Continuous Improvement, Manufacturing, Packaging, Lean Manufacturing, SPC, Six Sigma, Supply Chain, ISO, Spend Management, 5S, TPM, SMED, Quality Management, Value Stream Mapping, Process Engineering, Manufacturing Operations Management, Kaizen, Engineering, Factory, Supply Chain Management
Dejan Jovanovic Photo 39

Chief Technology Officer

Location:
Austin, TX
Industry:
Semiconductors
Work:
GLOBALFOUNDRIES - Austin, Texas Area since Jul 2012
Principal Member Technical Staff, Design Enablement
Freescale Semiconductor - Austin, Texas Oct 2010 - Sep 2012
Technology Manager, Senior Member Technical Staff
Freescale Semiconductor Feb 2003 - 2012
Senior Member Technical Staff
Motorola Inc - Santa Fe, New Mexico Area May 1997 - Feb 2003
Senior Member Technical Staff
Texas Instruments - Dallas, Texas Nov 1993 - May 1997
Member Technical Staff
Education:
University of Illinois at Urbana-Champaign 1989 - 1993
Ph.D., Electrical and Computer Engineering, Physics
University of Illinois at Urbana-Champaign 1987 - 1989
M.S., Electrical and Computer Engineering, Physics
Purdue University 1983 - 1987
Department; B.S, Electrical and Computer Engineering
Skills:
Semiconductors, Semiconductor Industry, Process Integration, Cmos, Simulations, Data Analysis, Sram, Perl, Semiconductor Process, Microelectronics, Design of Experiments, Nanotechnology, Physics, Thin Films, Silicon, Failure Analysis, Semiconductor Manufacturing, Statistics, C++, C, Software Development, System on A Chip, Mathematics, Device Physics, Computer Vision, 3D Visualization, Gpu Programming, Saas, Mobile Applications, Augmented Reality, Segmentation, Integrated Circuits, Integration
Languages:
English
French
Serbian
Dejan Jovanovic Photo 40

Editor In Chief

Location:
Chicago, IL
Industry:
Publishing
Work:
Balkan City Magazine
Editor In Chief
Skills:
Graphic Design, Commercial Photography, Portrait Photography, Photography
Languages:
English
Serbian
Bosnian
Certifications:
Grphic Design & Visualization - Pc Digital Certificate
Dejan Jovanovic Photo 41

Company Owner

Location:
Chicago, IL
Work:
Dj Photographics Ll
Company Owner
Dejan Jovanovic Photo 42

Dejan Jovanovic

Dejan Jovanovic Photo 43

Dejan Jovanovic

Dejan Jovanovic Photo 44

Dejan Jovanovic

Location:
United States

Publications & IP owners

Us Patents

Channel Orientation To Enhance Transistor Performance

US Patent:
7160769, Jan 9, 2007
Filed:
Oct 20, 2004
Appl. No.:
10/969108
Inventors:
Ted R. White - Austin TX, US
Alexander L. Barr - Crolles, FR
Dejan Jovanovic - Austin TX, US
Mariam G. Sadaka - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 21/336
H01L 29/78
US Classification:
438198, 438199, 438275, 257369, 257E21409, 257E29255
Abstract:
P channel transistors are formed in a semiconductor layer that has a (110) surface orientation for enhancing P channel transistor performance, and the N channel transistors are formed in a semiconductor layer that has a (100) surface orientation. To further provide P channel transistor performance enhancement, the direction of their channel lengths is selected based on their channel direction. The narrow width P channel transistors are preferably oriented in the direction. The wide channel width P channel transistors are preferably oriented in the direction.

Semiconductor Structure Having Strained Semiconductor And Method Therefor

US Patent:
7205210, Apr 17, 2007
Filed:
Feb 17, 2004
Appl. No.:
10/780143
Inventors:
Alexander L. Barr - Crolles, FR
Dejan Jovanovic - Austin TX, US
Mariam G. Sadaka - Austin TX, US
Ted R. White - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 21/30
H01L 21/46
US Classification:
438455, 257E21122
Abstract:
A first semiconductor structure has a silicon substrate, a first silicon germanium layer grown on the silicon, a second silicon germanium layer on the first silicon germanium layer, and a strained silicon layer on the second silicon germanium layer. A second semiconductor structure has a silicon substrate and an insulating top layer. The silicon layer of the first semiconductor structure is bonded to the insulator layer to form a third semiconductor structure. The second silicon germanium layer is cut to separate most of the first semiconductor structure from the third semiconductor structure. The silicon germanium layer is removed to expose the strained silicon layer where transistors are subsequently formed, which is then the only layer remaining from the first semiconductor structure. The transistors are oriented along the direction and at a 45 degree angle to the direction of the base silicon layer of the second silicon.

Method Of Making A Dual Strained Channel Semiconductor Device

US Patent:
7282402, Oct 16, 2007
Filed:
Mar 30, 2005
Appl. No.:
11/093801
Inventors:
Mariam G. Sadaka - Austin TX, US
Alexander L. Barr - Crolles, FR
Dejan Jovanovic - Austin TX, US
Shawn G. Thomas - Gilbert AZ, US
Ted R. White - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 21/8238
H01L 21/336
US Classification:
438221, 438197, 438199, 438230, 438202, 438258, 438303, 438207, 438218, 257E2163, 257E21631, 257E21632, 257E21633, 257E21634, 257E21635, 257E21636, 257E21637, 257E21638, 257E21639, 257E2164, 257E21641, 257E21642, 257E21643, 257E21644
Abstract:
According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.

Lateral Resonant Tunneling

US Patent:
5593908, Jan 14, 1997
Filed:
Jun 7, 1995
Appl. No.:
8/485249
Inventors:
Dejan Jovanovic - Dallas TX
John N. Randall - Richardson TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21265
H01L 2120
US Classification:
437 40
Abstract:
A resonant tunneling transistor (400) with lateral carrier transport through tunneling barriers (404, 408) grown as a refilling of trenches etched partially into a transverse quantum well (410) and defining a quantum wire or quantum dot (406). The fabrication methods include use of angled deposition to create overhangs at the top of openings which define sublithographic separations for tunneling barrier locations.

Lateral Resonant Tunneling Device Having Gate Electrode Aligned With Tunneling Barriers

US Patent:
5504347, Apr 2, 1996
Filed:
Oct 17, 1994
Appl. No.:
8/323983
Inventors:
Dejan Jovanovic - Dallas TX
John N. Randall - Richardson TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2906
US Classification:
257 25
Abstract:
A resonant tunneling transistor (400) with lateral carrier transport through tunneling barriers (404, 408) grown as a refilling of trenches etched partially into a transverse quantum well (410) and defining a quantum wire or quantum dot (406). The fabrication methods include use of angled deposition to create overhangs at the top of openings which define sublithographic separations for tunneling barrier locations.

Image Based Measurement System

US Patent:
2016037, Dec 22, 2016
Filed:
Jun 19, 2015
Appl. No.:
14/745325
Inventors:
Dejan Jovanovic - Austin TX, US
Keith Beardmore - Santa Fe NM, US
Kari Myllykoski - Austin TX, US
Mark O. Freeman - Snohomish WA, US
International Classification:
G06T 7/60
G06K 9/52
G06K 9/62
G06T 7/40
G06K 9/46
G06T 7/00
H04N 7/18
G06T 5/00
Abstract:
A Quantified Image Measurement System that creates accurate physical measurement data from digital pictures is disclosed. The system can use any image format and enhances the image file with measurement data and data transformation information that enables the creation of any type of geometrical or dimensional measurement from the stored photograph. This file containing the original digital image along with the supplemental data is referred to as a Quantified Image File or QIF. The QIF can be shared with other systems via email, cloud syncing or other types of sharing technology. Once shared, existing systems such as CAD applications or web/cloud servers can use the QIF and the associated QIF processing software routines to extract physical measurement data and use the data for subsequent processing or building geometrically accurate models of the objects or scene in the image. Additionally smart phones and other portable devices can use the QIF to make measurements on the spot or share between portable devices. In addition, the quantified image measurement system of this invention eliminates the need for capturing the image from any particular viewpoint by using multiple reference points and software algorithms to correct for any off-angle distortions.

Method And System For 3D Capture Based On Structure From Motion With Pose Detection Tool

US Patent:
2016026, Sep 8, 2016
Filed:
Mar 5, 2015
Appl. No.:
14/639912
Inventors:
Dejan JOVANOVIC - Austin TX, US
Keith Beardmore - Santa Fe NM, US
Kari Myllykoski - Austin TX, US
James H. Grotelueschen - Glen Ellyn WA, US
Mark O. Freeman - Snohomish WA, US
International Classification:
G06T 17/20
G06T 7/20
G06T 7/00
H04N 13/02
Abstract:
Method and System for 3D capture based on SFM with simplified pose detection is disclosed. This invention provides a straightforward method to directly track the camera's motion (pose detection) thereby removing a substantial portion of the computing load needed to build the 3D model from a sequence of images.

Multiple Template Improved 3D Modeling Of Imaged Objects Using Camera Position And Pose To Obtain Accuracy

US Patent:
2016013, May 12, 2016
Filed:
Nov 12, 2014
Appl. No.:
14/539924
Inventors:
Dejan Jovanovic - Austin TX, US
Keith Beardmore - Santa Fe NM, US
Kari Myllykoski - Austin TX, US
Mark O. Freeman - Snohomish WA, US
International Classification:
H04N 13/02
H04N 13/00
Abstract:
3D Modeling System and Apparatus for mobile devices with limited processing capability is disclosed. This invention uses the standard camera and computing resources available on consumer mobile devices such as smart phones. A light projector (e.g. laser line generator) is attached as an accessory to the mobile device or built as a part of the mobile device. Processing requirements are significantly reduced by including known object(s) or reference template(s) in the scene to be captured which are used to determine the pose/position of the camera relative to the object or scene to be modeled in a series of camera pose/position sequences. The position/pose of the camera and projector for each sequence is facilitated by image distortions of known dimensions of reference template or known object in a sequence of captured images.

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