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Derek D TamSanta Ana, CA

Derek Tam Phones & Addresses

Fountain Valley, CA   

Work

Company: Broadcom corporation Address: 5300 California Ave, Irvine, CA 92617 Phones: 949-9265000 Position: Xt 65642 Industries: Semiconductors and Related Devices

Mentions for Derek D Tam

Derek Tam resumes & CV records

Resumes

Derek Tam Photo 35

Derek Tam - Alhambra, CA

Work:
Schonbein's Microcirculation Laboratory Apr 2014 to 2000
Staff Research Associate
Mechanisms of Regulation for Serine Proteases Jun 2011 to 2000
intestine in rats at Professor Geert Schmid
CD for HIV Diagnostics Sep 2009 to Mar 2010
Senior Design Project
SURP Jun 2009 to Aug 2009
Fellow
UROP 2009 to 2009
Fellow
Education:
University of California - La Jolla, CA Mar 2014
M.S. in Bioengineering
University of California - Irvine, CA Jun 2010
B.S. in Biomedical Engineering
Derek Tam Photo 36

Derek Tam - San Diego, CA

Work:
Winter Quarter 2009 to 2000
Fellow
Schonbein's Microcirculation Laboratory Sep 2007 to 2000
Professor Geert Schmid
HIV Diagnostics Sep 2009 to Mar 2010
Senior Design Project
Summer Undergraduate Research Program Jun 2009 to Aug 2009
Fellow
Education:
University of California - Irvine, CA Jun 2010
B.S. in Biomedical Engineering
University of California - La Jolla, CA
M.S. in Bioengineering

Publications & IP owners

Us Patents

Thick Oxide P-Gate Nmos Capacitor For Use In A Phase-Locked Loop Circuit And Method Of Making Same

US Patent:
6828654, Dec 7, 2004
Filed:
Dec 27, 2001
Appl. No.:
10/026470
Inventors:
Derek Tam - Irvine CA
Jasmine Cheng - Irvine CA
Jungwoo Song - Irvine CA
Takayuki Hayashi - Irvine CA
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H01L 2900
US Classification:
257532, 327157, 327558
Abstract:
In a low-pass filter for a phase locked loop (PLL) circuit, a capacitor formed by an N-type substrate, a P-type region formed on the N-type substrate, a thick oxide formed over the P-type region, a P gate electrode formed over the thick oxide and coupled to a first voltage supply line, and P pick-up terminals formed in the P-type region adjacent the gate electrode and coupled to a second voltage supply line, whereby a gate-to-substrate voltage is maintained at less than zero volts to maintain a stable control voltage for the PLL.

Programmable Divider With Built-In Programmable Delay Chain For High-Speed/Low Power Application

US Patent:
6882189, Apr 19, 2005
Filed:
Oct 14, 2003
Appl. No.:
10/683262
Inventors:
Derek Tam - Irvine CA, US
Takayuki Hayashi - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03K021/00
US Classification:
327115, 327117, 327176, 377 47, 377 48
Abstract:
A programmable divider includes a synchronous counter configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices are coupled to the synchronous counter and configurable to receive the first output signals and correspondingly produce second output signals. Also included is a multiplexer that is configured to receive the second output signals and has an output coupled to an input of the synchronous counter. In the programmable divider, characteristics of the synchronous counter are selectable based upon a particular number of the logic devices configured.

Programmable Divider With Built-In Programmable Delay Chain For High-Speed/Low Power Application

US Patent:
7005898, Feb 28, 2006
Filed:
Sep 22, 2004
Appl. No.:
10/946172
Inventors:
Derek Tam - Irvine CA, US
Takayuki Hayashi - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03K 21/00
US Classification:
327115, 327117, 327176, 377 47, 377 48
Abstract:
A programmable divider includes a synchronous counter configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices are coupled to the synchronous counter and configurable to receive the first output signals and correspondingly produce second output signals. Also included is a multiplexer that is configured to receive the second output signals and has an output coupled to an input of the synchronous counter. In the programmable divider, characteristics of the synchronous counter are selectable based upon a particular number of the logic devices configured.

Fine Step And Large Gain Range Programmable Gain Amplifier

US Patent:
7098738, Aug 29, 2006
Filed:
Dec 24, 2003
Appl. No.:
10/744785
Inventors:
Derek Hing-Sang Tam - Irvine CA, US
Ardie Venes - Laguna Niguel CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03G 3/30
US Classification:
330284
Abstract:
A programmable gain amplifier with three stages uses fine steps, has a large gain range, and is monotonic. The first stage comprises several amplifiers, each including a resistive feedback loop. The feedback loop comprises a series of resistors, with each resistor acting as a tap. Since the number of resistors in the loop is unchanging, monotonicity and stability is guaranteed when resistance is increased using successive taps. A switch system connects two taps at a time to an interpolation stage. Each of these taps corresponds to a specific resistor level, and thus a gain level. The interpolation stage uses a plurality of current sources inside a feedback amplifier to control the interpolation, in order to provide fine gain steps.

Thick Oxide P-Gate Nmos Capacitor For Use In A Low-Pass Filter Of A Circuit And Method Of Making Same

US Patent:
7547956, Jun 16, 2009
Filed:
Oct 28, 2004
Appl. No.:
10/975090
Inventors:
Derek Tam - Irvine CA, US
Jasmine Cheng - Irvine CA, US
Jungwoo Song - Irvine CA, US
Takayuki Hayashi - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H01L 23/58
US Classification:
257532, 257368, 438307, 438379, 327157, 327558
Abstract:
A circuit with dielectric thicknesses is presented that includes a low-pass filter including one or more semiconductor devices having a thick gate oxide layer, while further semiconductor devices of the circuit have thin gate oxide layers. The low-pass filter semiconductor device includes an N-type substrate, a P-type region formed on the N-type substrate, a thick gate oxide layer formed over the P-type region, a P gate electrode formed over the thick gate oxide layer and coupled to a first voltage supply line, and P pick-up terminals formed in the P-type region adjacent the gate electrode and coupled to a second voltage supply line. The low-pass filter semiconductor device acts as a capacitor, whereby a gate-to-substrate voltage is maintained at less than zero volts to maintain a stable control voltage for the circuit.

Active Termination And Switchable Passive Termination Circuits

US Patent:
7982491, Jul 19, 2011
Filed:
Apr 8, 2009
Appl. No.:
12/384793
Inventors:
Joseph Aziz - Irvine CA, US
Andrew Chen - Redondo Beach CA, US
Derek Tam - Irvine CA, US
Agnes Neves Woo - Encino CA, US
Marcel Lugthart - Aliso Viejo CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03K 17/16
H03K 19/003
US Classification:
326 30, 326 34, 326 86
Abstract:
According to one exemplary embodiment, an active termination circuit includes at least one active termination branch, where the at least one active termination branch includes at least one transistor for providing an active termination output. The at least one active termination branch further includes an amplifier driving the at least one transistor, where the amplifier has a non-inverting input coupled to the active termination output via a feedback network. The amplifier controls a current flowing through the at least one transistor so as to provide the active termination output. The active termination output can be provided at a drain of the at least one transistor, where a source of the at least one transistor is coupled to ground through a degeneration transistor and a tail current sink.

Thick Oxide P-Gate Nmos Capacitor For Use In A Low-Pass Filter Of A Circuit And Method Of Making Same

US Patent:
8148219, Apr 3, 2012
Filed:
Jun 15, 2009
Appl. No.:
12/484652
Inventors:
Derek Tam - Irvine CA, US
Jasmine Cheng - Irvine CA, US
Jungwoo Song - Irvine CA, US
Takayuki Hayashi - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H01L 21/338
US Classification:
438177, 438307, 257288, 257E21623
Abstract:
A circuit with dielectric thicknesses is presented that includes a low-pass filter including one or more semiconductor devices having a thick gate oxide layer, while further semiconductor devices of the circuit have thin gate oxide layers. The low-pass filter semiconductor device includes an N-type substrate, a P-type region formed on the N-type substrate, a thick gate oxide layer formed over the P-type region, a Pgate electrode formed over the thick gate oxide layer and coupled to a first voltage supply line, and Ppick-up terminals formed in the P-type region adjacent the gate electrode and coupled to a second voltage supply line. The low-pass filter semiconductor device acts as a capacitor, whereby a gate-to-substrate voltage is maintained at less than zero volts to maintain a stable control voltage for the circuit.

Circuit For Digitally Controlling Line Driver Current

US Patent:
8183885, May 22, 2012
Filed:
Apr 8, 2009
Appl. No.:
12/384795
Inventors:
Joseph Aziz - Irvine CA, US
Andrew Chen - Redondo Beach CA, US
Derek Tam - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03K 19/094
US Classification:
326 86, 326 83, 327109, 341145
Abstract:
In one embodiment, a circuit for providing a tail current for a line driver includes an adjustable current source. The adjustable current source includes a number of current source cells coupled together in a parallel configuration, where the current source cells are configured to provide the tail current for the line driver in response to a digital control signal. The circuit can further include a digital core coupled to the adjustable current source, where the digital core provides the digital control signal. The digital control signal provides a number of bits, where each bit controls one of the current source cells. In one embodiment, a current source cell can comprise a number of current source sub-cells. The current source cells can be configured to provide the tail current for the line driver in response to the digital control signal when the line driver is operating in a class AB mode.

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